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Code Activity
15416 commits 101 branches 53 tags 48 MiB
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Author SHA1 Message Date
Martin Povišer
78382eaa6f libparse: Adjust whitespace 2024-08-13 18:47:36 +02:00
github-actions[bot]
4b9f452735 Bump version 2024-08-13 00:19:11 +00:00
Martin Povišer
8ce6219a34
Merge pull request #4528 from povik/bump-abc 
Bump ABC
 2024-08-12 15:53:16 +02:00
Martin Povišer
bcb995b506 Sync with yosys-experimental branch 2024-08-08 17:33:54 +02:00
Akash Levy
06f5743ac6 Removed submodule 2024-08-08 02:08:01 -07:00
Akash Levy
a66e32d471
Merge branch 'YosysHQ:main' into master 2024-08-08 01:38:27 -07:00
github-actions[bot]
77b2ae2e39 Bump version 2024-08-08 00:18:08 +00:00
Akash Levy
953f405a84
Merge branch 'YosysHQ:main' into master 2024-08-07 11:47:52 -07:00
Martin Povišer
4b5beb635f Pull ABC fix 2024-08-07 17:31:34 +02:00
Martin Povišer
ebffe37e4c Bump ABC 2024-08-07 15:54:03 +02:00
Martin Povišer
b1569de537
Merge pull request #4527 from povik/exec-newline 
exec: Add missing newline
 2024-08-07 13:04:48 +02:00
Martin Povišer
4c3203866f exec: Add missing newline 2024-08-07 13:02:00 +02:00
George Rennie
b6ceff2aab peepopt clockgateff: add testcase 2024-08-07 10:21:52 +01:00
George Rennie
236c69bed4 clk2fflogic: run peepopt -formalclk before processing design 
* this attempts to rewrite clock gating patterns into a form that is
  less likely to introduce combinational loops with clk2fflogic

* can be disabled with -nopeepopt which is useful for testing
  clk2fflogic
 2024-08-07 10:14:04 +01:00
George Rennie
2cb3b6e9b8 peepopt: add formal only peepopt to rewrite latches to ffs in clock gates 
* this is gated behind the -formalclk flag, which also disables the other
  synthesis focused optimizations
 2024-08-07 10:01:45 +01:00
github-actions[bot]
669f8b18f0 Bump version 2024-08-07 00:18:20 +00:00
Akash Levy
31d8d5de41
Merge branch 'YosysHQ:main' into master 2024-08-06 03:06:59 -07:00
Akash Levy
68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy
36fb6e08c1 Make muxpack faster 2024-08-06 02:26:57 -07:00
Akash Levy
7f5dcd270d
Merge branch 'YosysHQ:main' into master 2024-08-06 01:01:08 -07:00
Miodrag Milanovic
d08bf671b2 Next dev cycle 2024-08-06 09:48:35 +02:00
Miodrag Milanovic
80ba43d262 Release version 0.44 2024-08-06 09:42:28 +02:00
Miodrag Milanović
e5d8505349
Merge pull request #4523 from YosysHQ/emil/no-lto-lld 
Makefile: no LTO and lld by default
 2024-08-06 09:08:09 +02:00
github-actions[bot]
d2b5788674 Bump version 2024-08-06 00:18:14 +00:00
Akash Levy
24f38678ac NDEBUG doesn't do anything 2024-08-05 16:46:00 -07:00
Akash Levy
b4ae5e8574
Merge branch 'YosysHQ:main' into master 2024-08-05 11:02:17 -07:00
Emil J. Tywoniak
eeecb54532 Makefile: no LTO and lld by default 2024-08-05 19:28:09 +02:00
N. Engelhardt
01b99972b4
Merge pull request #4518 from YosysHQ/micko/sim_signal_names 
Set ranges on exported wires in VCD and FST
 2024-08-05 15:03:59 +02:00
Miodrag Milanovic
6d98418f3d Set ranges on exported wires in VCD and FST 2024-08-02 15:23:00 +02:00
Akash Levy
f7ffd73fa0 Fix opt_dff problem 2024-08-01 09:20:18 -07:00
Akash Levy
76db4e390b Smalledit 2024-08-01 00:04:50 -07:00
Akash Levy
9873315caa Update Verific 2024-07-31 22:40:15 -07:00
Akash Levy
c2da53be50 Fix gitignore 2024-07-30 23:10:28 -07:00
Akash Levy
bafce0ddee Revert SCC 2024-07-30 23:08:06 -07:00
Akash Levy
c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Roland Coeurjoly
7e34142965 Run nix build also on macos. Build with more logs 2024-07-30 22:47:30 +02:00
github-actions[bot]
c788484679 Bump version 2024-07-30 00:18:19 +00:00
Miodrag Milanović
3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Emil J
92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy 
cost: add keep_hierarchy pass with min_cost argument
 2024-07-29 16:33:08 +02:00
Miodrag Milanovic
405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
N. Engelhardt
9f869b265c
Merge pull request #4474 from tony-min-1/mchp 
Add PolarFire FPGA support
 2024-07-29 15:28:44 +02:00
N. Engelhardt
7c3666ff68
Merge pull request #4505 from YosysHQ/micko/ext_register 
Initialize extensions when Verific pass is registered
 2024-07-29 15:23:31 +02:00
Emil J
e21dd292fc
Merge pull request #4502 from YosysHQ/emil/build-opt-levels 
Release build configuration improvements
 2024-07-29 15:13:52 +02:00
Emil J. Tywoniak
af0c2fa659 Brewfile: add llvm for lld 2024-07-29 15:13:24 +02:00
Emil J
051d83205d
Merge pull request #4471 from georgerennie/hashlib_primes 
hashlib: Add some more primes
 2024-07-29 15:10:22 +02:00
Martin Povišer
61ae9f4e07
Merge pull request #4514 from YosysHQ/emil/proc_rom-src-test-2 
proc_rom: test src attribute on memories
 2024-07-29 13:58:19 +02:00
Emil J. Tywoniak
4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Emil J
49eaa108a5
Merge pull request #4425 from YosysHQ/emil/doc-sigmap 
sigmap: comments
 2024-07-29 10:18:44 +02:00
Emil J. Tywoniak
01fd72520f proc_rom: test src attribute on memories 2024-07-29 10:13:45 +02:00
Akash Levy
89630d3755
Merge branch 'YosysHQ:main' into master 2024-07-28 22:42:33 -07:00