Jannis Harder
4bb4b6c662
verific: Extend -sva-continue-on-err to handle FSM explosion
...
This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
2025-09-27 21:13:02 +02:00
Jannis Harder
83dd99efb7
verific: New -sva-continue-on-error import option
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This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
2025-09-24 18:58:54 +02:00
Robert O'Callahan
8b75c06141
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
Krystine Sherwin
017524d7a2
tests/verific: Don't ASAN verific
2025-06-28 11:33:18 +12:00
Krystine Sherwin
fa68299b25
tests/verific: Add chformal tests
2025-06-14 11:06:38 +12:00
Emil J
6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer
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test: every test everywhere all at once
2024-12-18 19:02:39 +01:00
Emil J. Tywoniak
6240aec433
test: restore verific handling, nicer naming
2024-12-13 10:24:47 +01:00
N. Engelhardt
378864d33b
bound attributes: handle vhdl null ranges
2024-12-12 11:42:39 +01:00
N. Engelhardt
03033ab6d4
add more tests for bounds attributes, fix attributes appearing in verilog
2024-12-11 16:11:02 +01:00
Miodrag Milanovic
05398889ad
Add verific verilog test cases for blackboxes
2024-12-06 16:13:25 +01:00
N. Engelhardt
8b0f665cc5
add setenv pass
2024-12-06 11:25:43 +01:00
Miodrag Milanovic
df391f5816
verific: fix blackbox regression and add test case
2024-11-08 14:57:04 +01:00
Roland Coeurjoly
bdc43c6592
Add left and right bound properties to wire. Add test. Fix printing
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for signed attributes
Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-09-10 12:52:42 +02:00
Miodrag Milanovic
d00843d436
Add -nordff to test
2024-02-06 10:36:30 +01:00
Miodrag Milanovic
1764c0ee3c
Fix verific clocking when no driver exist
2024-01-18 08:47:04 +01:00
N. Engelhardt
833b67af80
verific: import attributes on ports
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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
2023-10-20 18:31:41 +02:00
N. Engelhardt
1b6d1e9419
memory_libmap: look for ram_style attributes on surrounding signals
2023-10-19 19:23:35 +02:00
Martin Povišer
8222121164
verific: Add test of accurate semantics in memory inference
2023-09-18 16:37:15 +02:00
Jannis Harder
390d1c583a
verific: Fix enum_values support and signed attribute values
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This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
2023-03-15 09:51:36 +01:00
Miodrag Milanovic
d8cefec169
Added ranged case check
2023-02-27 09:24:04 +01:00
Miodrag Milanovic
53a4f0fb56
Add test example
2023-02-27 09:24:04 +01:00
