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mirror of https://github.com/YosysHQ/yosys synced 2025-04-07 18:05:24 +00:00
Code Activity
124 commits 94 branches 52 tags 62 MiB
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5 commits

Author SHA1 Message Date
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf 441e5fbfca Fixed a gcc compiler warning [-Wparentheses] 2013-03-03 22:45:06 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00