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4136 commits 95 branches 53 tags 45 MiB
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Author SHA1 Message Date
Clifford Wolf
51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
Clifford Wolf
12440fcc8f Add $lut support to Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-06 00:18:01 +02:00
Clifford Wolf
5d9d22f66d Add "verific -L <int>" option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 20:06:10 +02:00
Clifford Wolf
0b7a18470b Add "make ystests" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-30 12:26:26 +02:00
Miodrag Milanović
d36d11936f Add GCC to osx deps (#620) 
* Add GCC to osx deps

* Force gcc-7 install
 2018-08-28 17:17:33 +02:00
Clifford Wolf
cf2ea21899
Merge pull request #619 from mmicko/master 
Remove mercurial, since it is not needed anymore
 2018-08-28 13:37:11 +02:00
Miodrag Milanovic
92896a58be Remove mercurial, since it is not needed anymore 2018-08-28 13:11:41 +02:00
Clifford Wolf
373244c5ab
Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes 
Add support for modules.
 2018-08-28 12:04:49 +02:00
Jim Lawson
e217c6c52f Merge branch 'master' into firrtl+modules+shiftfixes 2018-08-27 12:13:04 -07:00
Jim Lawson
380c6f0e97 Remove unused functions. 2018-08-27 10:18:33 -07:00
Jim Lawson
604b5d4e20
Merge pull request #3 from YosysHQ/master 
merge with YosysHQ
 2018-08-27 10:09:39 -07:00
Clifford Wolf
ddc1761f1a Add "make coverage" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 14:22:21 +02:00
Clifford Wolf
9e845bd254 Add ENABLE_GCOV build option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 13:27:05 +02:00
Clifford Wolf
96d79878b9
Merge pull request #617 from mmicko/master 
static link flag on main executable
 2018-08-25 16:40:55 +02:00
Miodrag Milanovic
306a010e19 static link flag on main executable 2018-08-25 16:20:44 +02:00
Jim Lawson
93d19dc2fb Add support for module instances. 
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
 2018-08-23 14:35:11 -07:00
Clifford Wolf
4d269f9b25
Merge pull request #610 from udif/udif_specify_round2 
More specify/endspecify fixes
 2018-08-23 14:43:25 +02:00
Clifford Wolf
92c2a04e19
Merge pull request #614 from udif/pr_disable_dump_ptr 
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
 2018-08-23 14:41:41 +02:00
Udi Finkelstein
042b3074f8 Added -no_dump_ptr flag for AST dump options in 'read_verilog' 
This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
 2018-08-23 15:26:02 +03:00
Jim Lawson
2c0601eb6f
Merge pull request #1 from YosysHQ/master 
merge with YosysHQ master
 2018-08-22 08:42:34 -07:00
Clifford Wolf
408077769f Add "verific -work" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 17:22:24 +02:00
Clifford Wolf
4b02ee9162 Add Verific -work parameter 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 13:30:22 +02:00
Udi Finkelstein
fbfc677df3 Fixed all known specify/endspecify issues, without breaking 'make test'. 
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
 2018-08-20 17:27:45 +03:00
Udi Finkelstein
95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00
Clifford Wolf
05466790a6
Merge pull request #606 from cr1901/show-win 
`show` pass `-format` and `-viewer` improvements on Windows
 2018-08-19 15:25:46 +02:00
Clifford Wolf
519fe50b94
Merge pull request #608 from mmicko/master 
Static builds and cross-compilation support
 2018-08-18 19:17:42 +02:00
Miodrag Milanovic
75d1852943 no -fPIC for any static build 2018-08-18 19:17:02 +02:00
Miodrag Milanovic
443865ab87 respect DISABLE_ABC_THREADS if used 2018-08-18 18:21:28 +02:00
Miodrag Milanovic
45740236b6 Enable propagating ARCHFLAGS 2018-08-18 15:11:58 +02:00
Miodrag Milanovic
539053ab68 Added option to disable -fPIC on unsupported platforms 2018-08-18 14:14:17 +02:00
Miodrag Milanovic
3e20788c24 Added gcc-static for easier cross compilation 2018-08-18 14:00:55 +02:00
Clifford Wolf
620ebd3c6d
Merge pull request #575 from aman-goel/master 
Adds -expose option to setundef pass
 2018-08-18 13:22:39 +02:00
Aman Goel
83b41260f6 Revision to expose option in setundef pass 
Corrects indentation

Simplifications and corrections
 2018-08-18 09:08:07 +05:30
Aman Goel
61f002c908
Merge pull request #3 from YosysHQ/master 
Updates from official repo
 2018-08-18 08:18:40 +05:30
Clifford Wolf
e343f3e6d4 Add "verific -set-<severity> <msg_id>.." 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:49:17 +02:00
Clifford Wolf
0899a53bee Verific workaround for VIPER ticket 13851 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-16 11:31:19 +02:00
William D. Jones
7ce7ea2eb4 Update show pass documentation with Windows caveats. 2018-08-15 17:18:19 -04:00
William D. Jones
9f91c62348 Fix run_command() when using -format and -viewer in show pass. 2018-08-15 17:18:19 -04:00
Udi Finkelstein
28cfc75a90 A few minor enhancements to specify block parsing. 
Just remember specify blocks are parsed but ignored.
 2018-08-15 20:14:52 +03:00
Clifford Wolf
ce3dc3e01d
Merge pull request #605 from mmicko/master 
Changes for MXE configuration in order to compile
 2018-08-15 19:12:38 +02:00
Miodrag Milanovic
a5136c768b Changes for MXE configuration in order to compile 2018-08-15 19:08:45 +02:00
Clifford Wolf
ed32760d4a
Merge pull request #573 from cr1901/msys-64 
Add support for 64-bit builds using msys2 environment, use msys-provided `libpthread`.
 2018-08-15 14:20:10 +02:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override 
Consistent use of 'override' for virtual methods in derived classes.
 2018-08-15 14:05:38 +02:00
Clifford Wolf
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error 
Fix remaining log_file_error(); emit dependent file references in new…
 2018-08-15 14:01:34 +02:00
Clifford Wolf
dfc0c8ffc8
Merge pull request #576 from cr1901/no-resource 
Gate POSIX-only signals and resource module to only run on POSIX Pyth…
 2018-08-15 14:00:19 +02:00
Clifford Wolf
d70830a1be
Merge pull request #592 from japm48/master 
fix basys3 example
 2018-08-15 13:37:25 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Clifford Wolf
d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl 
Detect illegal port declaration, e.g input/output/inout keyword must …
 2018-08-15 13:14:23 +02:00
Clifford Wolf
1dd156f516 Fix use of signed integers in JSON back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-14 23:31:25 +02:00
Clifford Wolf
2353d28ff2
Merge pull request #602 from litghost/add_eblif_extension 
Map .eblif extension as blif.
 2018-08-14 12:47:41 +02:00