3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-11 11:43:38 +00:00
Commit graph

2 commits

Author SHA1 Message Date
Miodrag Milanovic 43030db5ff Leave only real black box cells 2018-12-02 11:57:50 +01:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00