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Code Activity
9506 commits 121 branches 59 tags 69 MiB
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Author SHA1 Message Date
Eddie Hung
0d347e1708 Replace log_assert() with meaningful log_error() 2019-06-28 11:28:29 -07:00
Eddie Hung
e44042a641 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:17:13 -07:00
Eddie Hung
fdf0e82472 Add missing CHANGELOG entries 2019-06-28 11:16:53 -07:00
Eddie Hung
b5f1bd0df1 Add missing CHANGELOG entries 2019-06-28 11:16:15 -07:00
Eddie Hung
c5b3830f73 Update CHANGELOG with -widemux 2019-06-28 11:12:41 -07:00
Eddie Hung
e852ec10fe Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:11:56 -07:00
Eddie Hung
4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung
4ef26d4755 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-28 11:09:42 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Eddie Hung
38d8806bd7 Add generic __builtin_bswap32 function 2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317 Also fix write_aiger for UB 2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb Fix more potential for undefined behaviour due to container invalidation 2019-06-28 09:51:43 -07:00
Eddie Hung
03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00
Clifford Wolf
74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-06-28 10:30:31 +02:00
Clifford Wolf
af74409749 Improve specify dummy parser, fixes #1144 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-28 10:21:16 +02:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master 
Optimizing DFFs whose initial value prevents their value from changing
 2019-06-28 08:30:18 +02:00
Gabriel L. Somlo
6f1c137989 tests: use optional ABCEXTERNAL when specified 
Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-27 23:00:13 -04:00
Eddie Hung
00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe Extraneous newline 2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung
550760cc72 Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-27 15:30:00 -07:00
Eddie Hung
a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung
312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung
137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Eddie Hung
fb30fcb7c5 Undo iterator based Module::remove() for cells, as containers will not 
invalidate
 2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic
3225bfb984 Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too 2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic
35fa7b3057 Fix memory leak when one of multiple DFF cells is removed in opt_rmdff 
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
 2019-06-27 22:02:12 +02:00
Eddie Hung
9a371cfba9 Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 12:53:23 -07:00
Eddie Hung
c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog 
tests: Check that Icarus can parse arch sim models
 2019-06-27 12:31:15 -07:00
Eddie Hung
1c79a32276 Merge branch 'xaig' into xc7mux 2019-06-27 11:55:11 -07:00
Eddie Hung
440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung
eab8384ec7 Grr 2019-06-27 11:53:42 -07:00
Eddie Hung
36f3cc9dcc Capitalisation 2019-06-27 11:50:12 -07:00
Eddie Hung
d5cfe341f9 Make CHANGELOG clearer 2019-06-27 11:50:12 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung
59434953e8 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-27 11:31:30 -07:00
Eddie Hung
83f143015b Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:31:19 -07:00
Eddie Hung
4d00e27ed7 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-27 11:23:30 -07:00
Eddie Hung
1237a4c116 Add warning if synth_xilinx -abc9 with family != xc7 2019-06-27 11:22:49 -07:00
Eddie Hung
469f98b6bd Remove unneeded include 2019-06-27 11:20:40 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
ab7c431905 Add simcells.v, simlib.v, and some output 2019-06-27 11:13:49 -07:00
Eddie Hung
18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung
760819e10d synth_xilinx -arch -> -family, consistent with older synth_intel 2019-06-27 07:24:47 -07:00