mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 08:24:35 +00:00
Code Activity
11286 commits 122 branches 59 tags 71 MiB
Commit graph

2 commits

Author SHA1 Message Date
Clifford Wolf
482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf
7a66b38c3e Added test cases for sat command 2014-02-04 13:43:34 +01:00