Miodrag Milanovic
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a689342207
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Remove trailing whitespaces
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2026-06-23 07:24:59 +02:00 |
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N. Engelhardt
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378864d33b
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bound attributes: handle vhdl null ranges
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2024-12-12 11:42:39 +01:00 |
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N. Engelhardt
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03033ab6d4
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add more tests for bounds attributes, fix attributes appearing in verilog
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2024-12-11 16:11:02 +01:00 |
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Roland Coeurjoly
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bdc43c6592
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Add left and right bound properties to wire. Add test. Fix printing
for signed attributes
Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
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2024-09-10 12:52:42 +02:00 |
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