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Author SHA1 Message Date
Marcelina Kościelnicka
5628f5a88f opt_mem_feedback: Respect write port priority. 2021-05-25 15:59:41 +02:00
Marcelina Kościelnicka
4858721637 kernel/mem: Add emulate_priority helper. 2021-05-25 12:25:58 +02:00
Marcelina Kościelnicka
e0736c1622 Add memory_narrow pass. 2021-05-25 03:04:13 +02:00
Marcelina Kościelnicka
47f958ce45 memory_share: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
9d5d5a48b1 opt_mem_feedback: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
c1a4730739 memory_map: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
1c903d3e47 sim: Add wide port support. 2021-05-25 02:57:32 +02:00
Marcelina Kościelnicka
69bf5c81c7 Reject wide ports in some passes that will never support them. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
35ee774ea8 kernel/mem: Add a Mem::narrow helper to split up wide ports. 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
8c1999aac1 kernel/mem: Emit support for wide ports in packed mode. 
Since the packed cell doesn't actually support wide ports yet, we just
auto-narrow them on emit.  The future packed cell will add
RD_WIDE_CONTINUATION and WR_WIDE_CONTINUATION parameters so the
transform will be trivially reversible for proper serialization.
 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
ff9713dd86 kernel/mem: Add model for wide ports. 
Such ports cannot actually be created or used yet, this just adds the
necessary plumbing in the helper.  Subsequent commits will gradually
add wide port support to various yosys passes.
 2021-05-25 02:07:25 +02:00
Marcelina Kościelnicka
95a39d3425 kernel/mem: Add priority_mask to model. 
This is going to be used to store arbitrary priority masks in the
future.  Right now, it is not supported by our cell library, so the
priority_mask is computed from port order on helper construction,
and discarded when emitted.  However, this allows us to already convert
helper-using passes to the new model.
 2021-05-25 00:38:20 +02:00
Marcelina Kościelnicka
835688bf80 opt_mem_feedback: Rewrite feedback path finding logic. 
Fixes #2766.
 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
b706adb809 opt_mem_feedback: Convert to Mem helpers. 2021-05-24 23:20:30 +02:00
Marcelina Kościelnicka
dbfd0b61e3 hashlib: Add a hash for bool. 2021-05-24 22:02:15 +02:00
Marcelina Kościelnicka
5488c69d2a Add a .mailmap file. 2021-05-24 17:37:29 +02:00
Miodrag Milanović
c9dc7d5928
Merge pull request #2779 from YosysHQ/mwk/nuke-travis 
Remove Travis CI.
 2021-05-24 17:24:01 +02:00
Marcelina Kościelnicka
c3e65a4ce0 Remove Travis CI. 
It has been replaced by GitHub Actions, and travis-ci.org is shutting
down in a few days anyway.
 2021-05-24 17:18:03 +02:00
Marcelina Kościelnicka
b6721aa9d8 backend/firrtl: Convert to use Mem helpers. 2021-05-24 14:00:33 +02:00
Marcelina Kościelnicka
ef4ddfacf3 github actions: Test on several gcc and clang versions on Linux. 
Fixes #2776.
 2021-05-24 02:20:16 +02:00
Marcelina Kościelnicka
df2b79ca76 memory_share: Use Mem helpers. 2021-05-23 23:16:12 +02:00
Marcelina Kościelnicka
afd5366fc2 extract_rdff: Add initvals parameter. 
This is not used yet, but will be needed when read port reset/initial
value support lands.
 2021-05-23 22:05:26 +02:00
Marcelina Kościelnicka
33513d923a btor: Use is_mem_cell in one more place. 2021-05-23 20:34:52 +02:00
Marcelina Kościelnicka
d905990d01 memory_share: Split off feedback path finding as a separate pass. 
memory_share is actually three passes in a trenchcoat.  Split off the
one that has the least in common with the other two as a separate pass.
 2021-05-23 18:30:39 +02:00
Marcelina Kościelnicka
1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
a23d9409e7 opt_mem: Remove write ports with const-0 EN. 
Fixes #2765.
 2021-05-23 14:30:56 +02:00
Marcelina Kościelnicka
039f4f48d5 memory_memx: Use Mem helper. 2021-05-22 22:31:07 +02:00
Marcelina Kościelnicka
c4cc888b2c kernel/rtlil: Extract some helpers for checking memory cell types. 
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
 2021-05-22 21:43:00 +02:00
Marcelina Kościelnicka
c7076495f1 kernel/mem: Add a check() function. 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
ff9e0394b8 kernel/mem: defer port removal to emit() 2021-05-22 21:42:53 +02:00
Marcelina Kościelnicka
8c734e07b8 memory_dff: Use Mem helper. 2021-05-21 02:26:27 +02:00
Miodrag Milanović
9420bde09f
Run VS build on PRs and each push 2021-05-20 19:21:34 +02:00
Marcelina Kościelnicka
25de8faf10 Bump version 2021-05-20 12:50:32 +02:00
Marcelina Kościelnicka
4240498f71 tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
Miodrag Milanovic
d8c5d6815c Visual Studio build action 2021-05-17 10:24:30 +02:00
gatecat
34a08750fa intel_alm: Fix illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
eb106732d9 intel_alm: Add global buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
gatecat
5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Rupert Swarbrick
3421979f00 Change the type of current_module to Module 
The current_module global is needed so that genRTLIL has somewhere to
put cells and wires that it generates as it makes sense of expressions
that it sees. However, that doesn't actually need to be an AstModule:
the Module base class is enough.

This patch should cause no functional change, but the point is that
it's now possible to call genRTLIL with a module that isn't an
AstModule as "current_module". This will be needed for 'bind' support.
 2021-05-13 23:44:48 -04:00
Rupert Swarbrick
51ed4a7149 Use range-based for loop in AST::process 
No functional change: just get rid of the explicit iterator and
replace (*it)-> with child->. It's even the same number of characters,
but is hopefully a little easier to read.
 2021-05-13 23:37:27 -04:00
Adam Greig
9e02786d39 Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. 2021-05-12 10:04:34 +01:00
Zachary Snow
4452080861 sv: check validity of package end label 2021-05-10 14:37:32 -04:00
Marcelina Kościelnicka
32a0ce9d68 blif: Use library cells' start_offset and upto for wideports. 
Fixes #2729.
 2021-05-08 15:50:03 +02:00
Marcelina Kościelnicka
a6081b46ce connect: Add -assert option, fix non-working sigmap. 
Should be useful for writing tests.
 2021-05-08 15:49:41 +02:00
Marcelina Kościelnicka
5c1e6a0e20 opt_dff: Fix NOT gates wired in reverse. 2021-05-04 21:03:40 +02:00
Miodrag Milanović
d061b0e41a
Merge pull request #2738 from mdko/xilinx-blif 
Fix use of blif name in synth_xilinx command
 2021-04-27 11:46:41 +02:00
Michael Christensen
67d6f3973b Fix use of blif name in synth_xilinx command 2021-04-27 02:29:52 -07:00
Claire Xen
86a6ac7623
Merge pull request #2737 from YosysHQ/claire/fix2736 
Remove duplicates from conns array in JSON front-end, fixes #2736
 2021-04-26 17:54:30 +02:00
Claire Xenia Wolf
58290c0c77 Remove duplicates from conns array in JSON front-end, fixes #2736 2021-04-26 16:32:12 +02:00
Claire Xen
a5adb00774
Merge pull request #2669 from YosysHQ/claire/ice40defaults 
Add input default assignments to iCE40 cell library
 2021-04-21 12:24:07 +02:00