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Author SHA1 Message Date
Clifford Wolf
7116621d22
Merge pull request #1076 from thasti/centos7-build-fix 
Fix pyosys-build on CentOS7
 2019-06-07 11:48:33 +02:00
Clifford Wolf
a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Stefan Biereigel
d018e02614 remove boost/log/exceptions.hpp from wrapper generator 2019-06-07 09:47:33 +02:00
Eddie Hung
88ae13e6a5 $__XILINX_MUX_ -> $__XILINX_SHIFTX 2019-06-06 15:32:36 -07:00
Eddie Hung
d3b7ae218b Fix muxcover and its techmapping 2019-06-06 15:31:18 -07:00
Eddie Hung
a8c49168fb Run muxpack and muxcover in synth_xilinx 2019-06-06 14:43:08 -07:00
Eddie Hung
7166dbe418 Remove abc_flop attributes for now 2019-06-06 14:35:38 -07:00
Eddie Hung
2223ca91b0 Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:22:10 -07:00
Eddie Hung
5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung
eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
Eddie Hung
0a66720f6f Fix warnings 2019-06-06 14:01:42 -07:00
Eddie Hung
ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung
dc7b8c4b94 More cleanup 2019-06-06 12:56:34 -07:00
Eddie Hung
978fda94f6 Fix spacing 2019-06-06 12:46:42 -07:00
Eddie Hung
d2172c6846 Non chain user check using next_sig 2019-06-06 12:44:50 -07:00
Eddie Hung
705388eb24 Add non exclusive test 2019-06-06 12:44:06 -07:00
Eddie Hung
83450a9489 Move muxpack from passes/techmap to passes/opt 2019-06-06 12:15:13 -07:00
Eddie Hung
3dd0682f29 Update doc 2019-06-06 12:11:59 -07:00
Eddie Hung
030f1d30e9 Add to CHANGELOG 2019-06-06 12:04:42 -07:00
Eddie Hung
b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung
5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung
3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
Eddie Hung
543dd11c7e Missing file 2019-06-06 11:03:45 -07:00
Eddie Hung
7bd1c664a6 Initial adaptation of muxpack from shregmap 2019-06-06 10:51:02 -07:00
tux3
88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Clifford Wolf
b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn 
Added support for parsing attributes on port connections.
 2019-06-06 12:34:05 +02:00
David Shah
30cedaca10
Merge pull request #1073 from whitequark/ecp5-diamond-iob 
ECP5: implement most Diamond I/O buffer primitives
 2019-06-06 11:22:49 +01:00
whitequark
f3a26730b6 ECP5: implement all Diamond I/O buffer primitives. 2019-06-06 10:18:33 +00:00
Clifford Wolf
e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070 
Fix typo in opt_rmdff causing register to be incorrectly removed
 2019-06-06 06:50:12 +02:00
Clifford Wolf
50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069 
Error out if no top module given before 'sim'
 2019-06-06 06:49:07 +02:00
Eddie Hung
fd8ef128bf Missing doc for -tech xilinx in shregmap 2019-06-05 14:21:44 -07:00
Eddie Hung
dd134914cc Error out if no top module given before 'sim' 2019-06-05 14:16:24 -07:00
Eddie Hung
feb2ddb52b Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
Eddie Hung
935df3569b shregmap -tech xilinx_static to handle INIT 2019-06-05 12:55:59 -07:00
Eddie Hung
72eda94a66 Continue support for ShregmapTechXilinx7Static 2019-06-05 12:33:55 -07:00
Eddie Hung
6ed15b7890 Update abc attributes on FD*E_1 2019-06-05 12:33:40 -07:00
Eddie Hung
67f744d428 Cleanup 2019-06-05 12:28:46 -07:00
Eddie Hung
2c18d530ea Call shregmap -tech xilinx_static 2019-06-05 12:28:26 -07:00
Eddie Hung
e473e74565 Revert "Move ff_map back after ABC for shregmap" 
This reverts commit 9b9bd4e19f.
 2019-06-05 11:53:06 -07:00
Eddie Hung
dfe9d95579 Add -tech xilinx_static 2019-06-05 11:14:14 -07:00
Eddie Hung
e1e37db860 Refactor to ShregmapTechXilinx7Static 2019-06-05 11:08:08 -07:00
Eddie Hung
45d1bdf83a shregmap -tech xilinx_dynamic to work -params and -enpol 2019-06-05 10:21:57 -07:00
Eddie Hung
a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065 
Suppress driver-driver conflict warning for unknown cell types
 2019-06-05 09:59:05 -07:00
Eddie Hung
bcc0a5d136 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-05 09:56:57 -07:00
Eddie Hung
b5aff1de04 Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux 2019-06-05 09:56:51 -07:00
Maciej Kurc
03e0d3a17c Fixed memory leak. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-05 10:42:43 +02:00
Clifford Wolf
f15b5e6309
Merge pull request #1066 from YosysHQ/clifford/fix1056 
Remove yosys_banner() from python wrapper init
 2019-06-05 10:37:39 +02:00
Clifford Wolf
b33176dafb Major rewrite of wire selection in setundef -init 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 10:26:48 +02:00
Clifford Wolf
6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00