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Author	SHA1	Message	Date
Clifford Wolf	de3ea9269a	updated default ABC command strings	2014-02-13 19:14:15 +01:00
Clifford Wolf	a123941618	Updated ABC	2014-02-13 18:56:36 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	b463907890	Removed double blanks in ABC default command sequences	2014-02-13 08:12:52 +01:00
Clifford Wolf	c6236c9e97	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-02-13 08:09:17 +01:00
Clifford Wolf	7664f5d92b	Updated ABC and some related changes	2014-02-13 08:07:08 +01:00
Clifford Wolf	6b210d2b6f	Merge pull request #26 from ahmedirfan1983/btor ... Btor	2014-02-12 23:46:58 +01:00
Clifford Wolf	08caa631dd	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-02-12 23:30:02 +01:00
Clifford Wolf	007bdff55d	Added support for functions returning integer	2014-02-12 23:29:54 +01:00
Ahmed Irfan	ac896c63e2	modified btor synthesis script for correct use of splice command.	2014-02-12 13:38:28 +01:00
Clifford Wolf	9ce7b0fc3b	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	2014-02-12 13:11:58 +01:00
Clifford Wolf	ab71bd0746	Updated ABC to rev e97a6e1d59b9	2014-02-12 08:35:42 +01:00
Clifford Wolf	0defc86519	renamed ilang "scope error" to "ilang error"	2014-02-11 19:17:07 +01:00
Ahmed Irfan	45e468114a	disabling splice command in the script	2014-02-11 15:43:03 +01:00
Ahmed Irfan	1d64b3e008	register output corrected	2014-02-11 13:28:05 +01:00
Ahmed Irfan	1a2dc48c2a	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor	2014-02-11 13:26:43 +01:00
Ahmed Irfan	e8f6b8f201	added concat and slice cell translation	2014-02-11 13:06:01 +01:00
Clifford Wolf	d2fd45949d	More Makefile cleanups	2014-02-11 12:58:08 +01:00
Clifford Wolf	4bd2d47e45	Improved "make manual" and "make clean"	2014-02-11 12:55:58 +01:00
Clifford Wolf	fb186e6299	Improved ilang parser error messages	2014-02-09 15:35:31 +01:00
Clifford Wolf	d229324420	fixed a bug in subcircuit library with cells that have connections to itself	2014-02-09 15:27:58 +01:00
Clifford Wolf	38469e7686	Various improvements in expose command (added -sep and -cut)	2014-02-09 11:07:46 +01:00
Clifford Wolf	b6f33576d5	Added delete {-input|-output|-port}	2014-02-09 10:03:26 +01:00
Clifford Wolf	b3b5fac191	Bugfix in delete command	2014-02-09 09:34:58 +01:00
Clifford Wolf	039bb456cc	Added test cases for expose -evert-dff	2014-02-08 21:31:56 +01:00
Clifford Wolf	85914c36e5	Fixed handling of async reset in expose -evert-dff	2014-02-08 21:26:40 +01:00
Clifford Wolf	db86aaa07d	Build fixes for log cmd	2014-02-08 21:21:51 +01:00
Clifford Wolf	c06de50f05	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-02-08 21:08:46 +01:00
Clifford Wolf	0935e20003	Implemented expose -evert-dff	2014-02-08 21:08:38 +01:00
Clifford Wolf	793290a304	Merge pull request #24 from hansiglaser/master ... added "log" command	2014-02-08 20:02:32 +01:00
Johann Glaser	af14bb5f65	added "log" command	2014-02-08 19:19:32 +01:00
Clifford Wolf	8f9c707a4c	Improved checking of internal cell conventions	2014-02-08 19:13:49 +01:00
Clifford Wolf	7f52c18a22	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	2014-02-08 19:13:19 +01:00
Clifford Wolf	926fa61119	Added various new options to splice command	2014-02-08 16:37:18 +01:00
Clifford Wolf	0c11d04144	Added %a select operator	2014-02-08 16:31:38 +01:00
Clifford Wolf	6644f80d97	Moved some passes to other source directories	2014-02-08 14:39:15 +01:00
Clifford Wolf	03ee63ff80	Added support for "keep" attribute to abc pass	2014-02-08 14:25:29 +01:00
Clifford Wolf	82c98bbbe6	Added opt -purge (frontend to opt_clean -purge)	2014-02-08 14:21:34 +01:00
Clifford Wolf	922d1c9520	Only count non-trivial attributes when findinf master signal in opt_clean	2014-02-08 14:21:04 +01:00
Clifford Wolf	669a6e462d	Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output	2014-02-08 12:27:38 +01:00
Clifford Wolf	2c51619c2b	Now also move net labes to the right position in splice cmd	2014-02-08 00:06:00 +01:00
Clifford Wolf	274bcef66c	Improved detection of primary wire for a signal in opt_clean	2014-02-07 23:50:17 +01:00
Clifford Wolf	244e8ce1f4	Added splice command	2014-02-07 20:30:56 +01:00
Clifford Wolf	08aa1062b4	Added log_header() to splitnets	2014-02-07 19:51:15 +01:00
Clifford Wolf	d85a6bf5d3	Added $slice and $concat to CellTypes list	2014-02-07 19:50:44 +01:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	a1ac710ab8	Stronger checking of internal cells	2014-02-07 17:39:35 +01:00
Clifford Wolf	99b1e9ee56	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	2014-02-07 16:36:37 +01:00
Clifford Wolf	a51a3fa2d2	Added echo command	2014-02-07 14:17:00 +01:00
Clifford Wolf	366dcd3abf	Fixed use of "cmd_error" in passes/cmds/design.cc	2014-02-07 14:16:42 +01:00