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8 commits

Author SHA1 Message Date
Emil J. Tywoniak
54742cd718 ffinit: an x init bit is the absence of a value, not a conflict 
Two wires whose init bits map to the same representative are legal --
they are connected -- and each extra alias makes it likelier. Today the
first one recorded wins and any later disagreement is a hard error, even
when one of the two is 1'x, which says nothing at all
(arch/ice40/bug1644: `\DAC1_i2s.left_1 [0] = 1'0 != 1'x`).

An x now loses to a defined value and never reports a conflict; two
defined values that disagree still do.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
 2026-07-21 16:52:31 +02:00
Robert O'Callahan
5ff7d344c9 Add FfInitVals::set_parallel() method 
We'll use this later in the PR.
 2026-03-06 02:03:21 +00:00
Robert O'Callahan
6dc9a8bacf Update kernel to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan
2654bd5355 Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC. 
This does not scale when we run ABC thousands of times in a single AbcPass.
 2025-08-14 22:29:45 +00:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Marcelina Kościelnicka
1eea06bcc0 Add new helper class for merging FFs into cells, use for memory_dff. 
Fixes #1854.
 2021-05-23 14:46:59 +02:00
Marcelina Kościelnicka
773b056ffb ffinit: Fortify the code a bit. 
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
 2020-07-28 17:21:15 +02:00
Marcelina Kościelnicka
022af4f0ca Add utility module for dealing with init attributes. 2020-07-23 20:49:48 +02:00