Richard Herveille
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2893938355
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Removed SystemVerilog module end label
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2024-03-19 01:31:36 +01:00 |
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Richard Herveille
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2d11c5e2f8
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removed comment
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2024-03-15 01:48:06 +01:00 |
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Richard Herveille
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58b1522a20
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Added DSP macros
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2024-03-06 02:45:29 +01:00 |
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Richard Herveille
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b16cdaab35
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dsp_map for MAX10
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2024-03-06 02:43:30 +01:00 |
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Claire Xenia Wolf
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72787f52fc
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Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
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Marcelina Kościelnicka
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3209c0762a
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intel: Use dfflegalize.
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2020-07-13 19:21:05 +02:00 |
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Marcelina Kościelnicka
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88e7f90663
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Update dff2dffe, dff2dffs, zinit to new FF types.
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2020-06-23 18:24:53 +02:00 |
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Marcelina Kościelnicka
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aee439360b
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Add force_downto and force_upto wire attributes.
Fixes #2058.
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2020-05-19 01:42:40 +02:00 |
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c60k28
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efed2420d6
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Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
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2018-03-31 22:48:47 -06:00 |
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Larry Doolittle
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50bcd9a728
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Clean whitespace and permissions in techlibs/intel
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2017-10-05 16:23:49 +02:00 |
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dh73
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cbaba62401
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Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
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2017-10-01 11:04:17 -05:00 |
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