282 commits

Author	SHA1	Message	Date
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	160adccca2	Fixed the fix for propagation of width hints for $signed() and $unsigned()	2013-11-07 03:01:28 +01:00
Clifford Wolf	7fe13faefa	Fixed propagation of width hints for $signed() and $unsigned()	2013-11-06 22:41:21 +01:00
Clifford Wolf	baeca48a24	Additional fixes for undef propagation in concat and replicate ops	2013-11-06 21:16:54 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	472117d532	further improved early width and sign detection in ast simplifier	2013-11-04 06:04:42 +01:00
Clifford Wolf	d2b083f5cb	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	2013-11-03 18:56:45 +01:00
Clifford Wolf	ada80545fa	Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)	2013-11-02 21:13:01 +01:00
Clifford Wolf	943329c1dc	Various ast changes for early expression width detection (prep for constfold fixes)	2013-11-02 13:00:17 +01:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Clifford Wolf	0003743432	Fixed width and sign detection for ** operator	2013-08-19 20:58:01 +02:00
Clifford Wolf	759852914d	Added support for "2**n" shifter encoding	2013-08-12 14:47:50 +02:00
Clifford Wolf	c8763301b4	Added $div and $mod technology mapping	2013-08-09 17:09:24 +02:00
Clifford Wolf	3650fd7fbe	More fixes in ternary op sign handling	2013-07-12 13:13:04 +02:00
Clifford Wolf	ded769c98c	Fixed sign handling in ternary operator	2013-07-12 01:15:37 +02:00
Clifford Wolf	b380c8c790	Another vloghammer related bugfix	2013-07-11 19:24:59 +02:00
Clifford Wolf	ed62fcdbe2	Fixed sign propagation in bit-wise operators	2013-07-09 23:53:55 +02:00
Clifford Wolf	5dab327b30	More fixes in ast expression sign/width handling	2013-07-09 23:41:43 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	e8da3ea7b6	Fixed another bug found using vloghammer	2013-07-07 16:49:30 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	a5c30183b5	Sign-extension related fixes in SatGen and AST frontend	2013-06-10 17:10:06 +02:00
Clifford Wolf	59dd02baa2	Fixes and improvements in AST const folding	2013-06-10 13:56:03 +02:00
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Clifford Wolf	e0c408cb4a	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
Clifford Wolf	f1a2fd966f	Now only use value from "initial" when no matching "always" block is found	2013-03-31 11:51:12 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	6a382f2aba	Fixed handling of unconditional generate blocks	2013-03-26 09:44:54 +01:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00