Aki-nyan
3048feb281
Merge 42e4610e3a into 47ca09a016
2025-10-08 07:34:47 +03:00
Robert O'Callahan
1a367b907c
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
Robert O'Callahan
f65ca488ec
Update frontends to avoid bits()
2025-09-16 03:17:23 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
...
There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
George Rennie
4a057b3c44
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang
2024-11-05 12:36:31 +13:00
Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
Roland Coeurjoly
27c1432253
Remove log
2024-08-21 14:28:42 +01:00
Roland Coeurjoly
91e3773b51
Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting
2024-08-21 14:28:42 +01:00
Aki Van Ness
9ffaae91ff
frontend: rtlil: imposed a hard limit for wire width of 2^24 ( closes #1206 )
2022-09-15 05:30:41 -04:00
Zachary Snow
fbd70f28f0
Specify minimum bison version 3.0+
...
Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous
release). Ideally, we would require "3" rather than "3.0" to give a
better error message, but bison 2.3, which still ships with macOS, does
not support major-only version requirements. With this change, building
with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14:
require bison 3.0, but have 2.3`.
2021-10-01 21:18:33 -06:00
Marcelina Kościelnicka
009940f56c
rtlil: Make Process handling more uniform with Cell and Wire.
...
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
2021-07-12 00:47:34 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
whitequark
015b476e56
rtlil: remove dotted identifiers.
...
No one knows where they came from and they never did anything useful.
2020-11-25 16:47:20 +00:00
whitequark
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
...
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
