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Code Activity
19210 commits 135 branches 69 tags 61 MiB
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1801 commits

Author SHA1 Message Date
nella
9143178343 Merge liberty files into stripped scl files. 2026-04-23 12:43:43 +02:00
Emil J. Tywoniak
b4c081c70b abc: fix deferred logs 2026-04-17 13:35:47 +02:00
nella
4506dffa9f Fix use after free. 2026-04-13 12:48:05 +02:00
nella
fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella
c3c577f333 Fix test cases. 2026-04-13 12:48:05 +02:00
nella
135812ab02 Further CSA cleanup. 2026-04-13 12:48:05 +02:00
nella
847a8941e9 Clang-Format CSA tree. 2026-04-13 12:48:05 +02:00
nella
a02c238874 Consolidate Wallace from booth and CSA. 2026-04-13 12:48:05 +02:00
nella
4bbffecf98 Invert. 2026-04-13 12:48:05 +02:00
nella
42c309347b Clarify. 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak
b6d656e932 csa_tree: move to techmap 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak
41b69df2cb abc_new: stable TopoSort 2026-04-06 15:09:52 +02:00
AdvaySingh1
aea16d3888 Removed -filter_non_trigger_outputs functionality 2026-03-31 10:12:21 -07:00
AdvaySingh1
8aebec79a8 Added -filter_non_trigger_outputs knob 2026-03-27 15:41:44 -07:00
AdvaySingh1
ad6546b05e Revert "Update passes/techmap/abc.cc" 
This reverts commit 20cf9fb461.
 2026-03-27 14:53:38 -07:00
Advay Singh
20cf9fb461
Update passes/techmap/abc.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-03-27 12:45:57 -07:00
AdvaySingh1
f7a9af5252 Make the signal_map flag optional 2026-03-24 14:39:21 -07:00
Emil J
b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
AdvaySingh1
e2a641f5a8 Added support for printing the cdc map file 2026-03-20 11:32:06 -07:00
AdvaySingh1
59dd03973e Added printing differnt clock domains in signal map 2026-03-20 10:37:47 -07:00
AdvaySingh1
52fad78b40 Removed is_port for non-trigger outputs. TODO: add a flag which does this so POs are only those ones 2026-03-19 09:23:12 -07:00
Lofty
f560cba952
Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 
abc9: remove -fast [sc-269]
 2026-03-19 08:41:45 +00:00
Lofty
27210627e5 abc9: remove -fast 2026-03-19 07:30:23 +00:00
Lofty
8d1d5a25e5
Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2 
abc: remove -S [sc-269]
 2026-03-19 07:26:54 +00:00
Lofty
05de1c4ae2
Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4 
abc9: remove abc9.if.C [sc-269]
 2026-03-19 07:26:37 +00:00
AdvaySingh1
dc73249d8f Added support for printing the signal map 2026-03-18 16:23:41 -07:00
Emil J. Tywoniak
7aaa0621d3 constmap: error if no -cell set 2026-03-19 00:01:14 +01:00
Lofty
f9d930ba5a
Revert "abc: remove -fast [sc-269]" 2026-03-18 17:55:17 +00:00
Lofty
e05ed6b850
Merge pull request #5758 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast [sc-269]
 2026-03-18 15:09:36 +00:00
Lofty
0b3f103745 abc: remove -S 2026-03-18 14:40:23 +00:00
Lofty
93c762c7c1 abc9: remove abc9.if.C 2026-03-18 14:27:27 +00:00
Lofty
926814f1e4 abc9: cleanup commented code 2026-03-18 14:16:31 +00:00
Lofty
0ea739b7d9 abc: remove -fast 2026-03-18 14:15:42 +00:00
Lofty
e78690fc47 abc9_exe: fix typo 2026-03-18 11:44:13 +00:00
AdvaySingh1
e2b71b0d55 Added -word arg 2026-03-04 14:51:47 -08:00
AdvaySingh1
26adc17fd7 Revert "Changed to for chacterization" 
Removing changing _DFF_ to dff for chacterization
 2026-03-04 10:43:53 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
4ab22cbb97 abc: use newcelltypes 2026-03-04 12:22:14 +01:00
Akash Levy
96104b4431 Merge branch 'main' into sat_clkgate 2026-03-03 20:57:42 -08:00
Tianji Liu
750d536bba abc: new option to pass ABC read_lib args 2026-03-04 11:24:24 +08:00
Akash Levy
7d96a7f73c Update aigmap to go a lot faster using aig template cache and uniquify cache 2026-03-01 22:35:06 -08:00
Akash Levy
b03f73653f Update abc to fix bug 2026-03-01 21:43:26 -08:00
AdvaySingh1
877e97de06 Changed to for chacterization 2026-02-27 15:23:50 -08:00
AdvaySingh1
90aa1cc016 Checked out main passes/techmap/clockgate.cc for source attributes and removed logging 2026-02-27 12:24:31 -08:00
Andrew Pullin
5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
AdvaySingh1
ec537b189f Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:50 -08:00
AdvaySingh1
8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify 
abc9: verify post-mapping equivalence by default
 2026-02-20 13:41:11 +01:00
AdvaySingh1
d9867fc7c7 Merge branch 'main' into sat_clkgate 2026-02-19 09:43:22 -08:00