mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 08:24:35 +00:00
Code Activity
15617 commits 122 branches 59 tags 71 MiB
Commit graph

5 commits

Author SHA1 Message Date
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
3209c0762a intel: Use dfflegalize. 2020-07-13 19:21:05 +02:00
Marcelina Kościelnicka
88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka
aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Dan Ravensloft
eab3272cde synth_intel: cyclone10 -> cyclone10lp 2019-12-10 13:47:58 +00:00
Renamed from techlibs/intel/cyclone10/cells_map.v (Browse further)