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13 commits

Author SHA1 Message Date
Krystine Sherwin
2d6738bb10
qlf_tests: minor adjustment
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 09:38:48 +13:00
N. Engelhardt
c2fc33f0eb fix test setup for synth_quicklogic memory tests 2023-12-01 14:03:07 +01:00
N. Engelhardt
190cbd54b1 fix test setup for synth_quicklogic memory tests 2023-12-01 10:47:39 +01:00
Krystine Sherwin
5634d98ccb
attempting to sim split memory tests
and failing
2023-12-01 21:16:58 +13:00
Krystine Sherwin
d9d54e66c7
QLF_TDP36K: asymmetric simulation tests 2023-12-01 20:47:39 +13:00
Krystine Sherwin
7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests
Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-01 17:00:15 +13:00
Krystine Sherwin
7a659bdd26
QLF_TDP36K: parameterised sim test gen
Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-01 16:26:00 +13:00
Krystine Sherwin
f810bd88f5 quicklogic: wildcard asymmetric memory tests 2023-11-30 17:33:13 +01:00
Krystine Sherwin
cdb20baf1f quicklogic: testing port widths on split rams 2023-11-30 17:33:13 +01:00
Krystine Sherwin
4c03c84fa7 quicklogic: testing 1:4 assymetric memory 2023-11-30 17:33:13 +01:00
Krystine Sherwin
a1073c706e quicklogic: fix double width read 2023-11-30 17:33:13 +01:00
Krystine Sherwin
fbf8607b97 quicklogic: Testing split TDP36K
Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-11-30 17:33:13 +01:00
Krystine Sherwin
0cd67ce473 quicklogic: Initial blockram tests
Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-11-30 17:33:13 +01:00