211 commits

Author	SHA1	Message	Date
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Clifford Wolf	ed0e2f7a6f	Added log_assert() api	2013-05-24 14:38:36 +02:00
Clifford Wolf	8f2d90de4f	Fixed handling of positional module parameters	2013-04-26 14:40:25 +02:00
Clifford Wolf	453a29c9f6	Only use sha1 checksums for names of parametric modules when the verbose form is to long	2013-04-26 13:13:58 +02:00
Clifford Wolf	f1a2fd966f	Now only use value from "initial" when no matching "always" block is found	2013-03-31 11:51:12 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00