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Author SHA1 Message Date
Krystine Sherwin
376f746bc9 analogdevices: Native LUTRAM primitives 2026-03-05 05:37:12 +00:00
Lofty
30a03886a5 analogdevices: LUTRAM config 2026-03-05 05:37:12 +00:00
Lofty
ae5325fe53 analogdevices: update timing model 2026-03-05 05:37:12 +00:00
Lofty
c4bec4e8b8 I thought I removed this... 2026-03-05 05:37:12 +00:00
Lofty
85eb07d14d analogdevices: user retargeting 2026-03-05 05:37:12 +00:00
Lofty
c9f6d7b2d4 analogdevices: more housekeeping 2026-03-05 05:37:12 +00:00
Lofty
f659cbd159 analogdevices: remove some extra cells! 2026-03-05 05:37:12 +00:00
Lofty
6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Lofty
4f2f064262 synth_analogdevices: remove scopeinfo cells 2026-03-05 05:37:12 +00:00
Lofty
d5ea7f7016 Create synth_analogdevices 2026-03-05 05:37:12 +00:00
Lofty
4caffa7ebd
Merge pull request #5725 from yrabbit/disable-wm-2 
GOWIN. Disable read-before-write mode.
 2026-03-05 05:36:28 +00:00
Andrew Pullin
6ac8c8cb05 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
 2026-03-04 21:34:40 -08:00
YRabbit
26dc01102e GOWIN. Disable read-before-write mode. 
According to the latest documentation from GOWIN -
"UG285-1.4E Gowin BSRAM & SSRAM User Guide"

The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A
series) does not support the read-before-write mode (WRITE_MODE = 2)

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-03-05 09:17:37 +10:00
abhinavputhran
94c789e9c8 setundef: respect selection for cells, processes, and connections 
Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.

Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.

Fixes #5624
 2026-03-04 17:48:35 -05:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
6485a13809 newcelltypes: mark header unstable 2026-03-04 15:17:26 +01:00
Miodrag Milanović
3bc26ff4d0
Merge pull request #5723 from YosysHQ/micko/merge_queue 
CI: add support for merge queue
 2026-03-04 13:18:09 +01:00
nella
16b1a914f1 Aiger use defines for known ops. 2026-03-04 12:39:45 +01:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
b8ee0803ab Remove todo. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
nella
cae54a4c7b Aiger use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b newcelltypes: extend testing 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
0284595e9c celltypes: fix absurd eval declarations 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
793a3513c6 newcelltypes: use unordered_map 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955 pyosys: disable test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
661fcb24cb newcelltypes: fix MSVC build 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
f594014bef newcelltypes: proper bounds for unit test 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
12412d1fa5 register: use newcelltypes 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
5216d32d1b yosys: use newcelltypes for yosys_celltypes 2026-03-04 12:22:47 +01:00
Emil J. Tywoniak
7a5c303ccd backends: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
c3ed884bc4 drivertools: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
665b6eeb4a aiger2: add TODO 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
4ab22cbb97 abc: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
d91e1c8607 newcelltypes: test against builtin_ff_cell_types 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
31b86ebc2e newcelltypes: comment 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
8e17fb0266 consteval: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a0f87dc2d1 modtools: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a9463d1aee newcelltypes: fix non-cells 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
e3f9911e33 newcelltypes: refactor 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3212dfaf1f newcelltypes: fix unit test 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
2d7d6ca10b newcelltypes: unit test 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
7e9e88c2ec newcelltypes: bounds check 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a61455645d newcelltypes: init 2026-03-04 12:22:14 +01:00