777 commits

Author	SHA1	Message	Date
Clifford Wolf	e5d42ebb4d	Added $display %m support, fixed mem leak in $display, fixes #128	2016-03-19 11:51:13 +01:00
Clifford Wolf	ef4207d5ad	Fixed localparam signdness, fixes #127	2016-03-18 12:15:00 +01:00
Clifford Wolf	b6d08f39ba	Set "nosync" attribute on internal task/function wires	2016-03-18 10:53:29 +01:00
Clifford Wolf	bcc873b805	Fixed some visual studio warnings	2016-02-13 17:31:24 +01:00
Rick Altherr	34969d4140	genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()	2016-01-31 09:20:16 -08:00
Clifford Wolf	c86fbae3d1	Fixed handling of re-declarations of wires in tasks and functions	2015-11-23 17:09:57 +01:00
Clifford Wolf	7ae3d1b5a9	More bugfixes in handling of parameters in tasks and functions	2015-11-12 13:02:36 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	e51dcc83d0	Fixed complexity of assigning to vectors in constant functions	2015-10-01 12:15:35 +02:00
Clifford Wolf	9caeadf797	Fixed detection of unconditional $readmem[hb]	2015-09-30 15:46:51 +02:00
Clifford Wolf	f9d7df0869	Bugfixes in $readmem[hb]	2015-09-25 13:49:48 +02:00
Clifford Wolf	b2544cfcf7	Fixed segfault in AstNode::asReal	2015-09-25 12:38:01 +02:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	1b8cb9940e	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	2015-09-24 11:21:20 +02:00
Clifford Wolf	089c1e176f	Bugfix in handling of multi-dimensional memories	2015-09-23 07:56:17 +02:00
Clifford Wolf	559929e341	Warning for $display/$write outside initial block	2015-09-23 07:16:03 +02:00
Clifford Wolf	6176f4d081	Fixed multi-level prefix resolving	2015-09-22 20:52:02 +02:00
Andrew Zonenberg	c469f22144	Improvements to $display system task	2015-09-19 10:33:37 +02:00
Clifford Wolf	9db05d17fe	Added AST_INITIAL checks for $finish and $display	2015-09-18 09:50:57 +02:00
Andrew Zonenberg	7141f65533	Initial implementation of $display()	2015-09-18 09:36:46 +02:00
Andrew Zonenberg	e446e651cb	Initial implementation of $finish()	2015-09-18 09:30:25 +02:00
Clifford Wolf	eb38722e98	Fixed handling of memory read without address	2015-08-22 14:46:42 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Larry Doolittle	022f570563	Keep gcc from complaining about uninitialized variables	2015-08-14 23:26:49 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	4513ff1b85	Fixed nested mem2reg	2015-07-29 16:37:08 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	13983e8318	Fixed handling of parameters with reversed range	2015-06-08 14:03:06 +02:00
Clifford Wolf	99b8746d27	Fixed signedness of genvar expressions	2015-05-29 20:08:00 +02:00
Clifford Wolf	422794c584	Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()	2015-03-01 11:20:22 +01:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	d5ce9a32ef	Added deep recursion warning to AST simplify	2015-02-20 10:33:20 +01:00
Clifford Wolf	dc1a0f06fc	Parser support for complex delay expressions	2015-02-20 10:21:36 +01:00
Clifford Wolf	c2ba4fb2fd	Convert floating point cell parameters to strings	2015-02-18 23:35:23 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	7f1a1759d7	Added "read_verilog -nomeminit" and "nomeminit" attribute	2015-02-14 11:21:12 +01:00
Clifford Wolf	a8e9d37c14	Creating $meminit cells in verilog front-end	2015-02-14 10:49:30 +01:00
Clifford Wolf	cd919abdf1	Added AstNode::simplify() recursion counter	2015-02-13 12:33:12 +01:00
Clifford Wolf	234a45a3d5	Ignore explicit assignments to constants in HDL code	2015-02-08 00:58:03 +01:00
Clifford Wolf	c8305e3a6d	Fixed a bug with autowire bit size ... (removed leftover from when we tried to auto-size the wires)	2015-02-08 00:48:23 +01:00
Clifford Wolf	2a9ad48eb6	Added ENABLE_NDEBUG makefile options	2015-01-24 12:16:46 +01:00
Clifford Wolf	df9d096a7d	Ignoring more system task and functions	2015-01-15 13:08:19 +01:00
Clifford Wolf	a588a4a5c9	Fixed handling of "input foo; reg [0:0] foo;"	2015-01-15 12:53:12 +01:00
Clifford Wolf	8e8e791fb5	Consolidate "Blocking assignment to memory.." msgs for the same line	2015-01-15 12:41:52 +01:00
Clifford Wolf	eefe78be09	Fixed memory->start_offset handling	2015-01-01 12:56:01 +01:00
Clifford Wolf	0bb6b24c11	Added global yosys_celltypes	2014-12-29 14:30:33 +01:00
Clifford Wolf	90bc71dd90	dict/pool changes in ast	2014-12-29 03:11:50 +01:00
Clifford Wolf	137f35373f	Changed more code to dict<> and pool<>	2014-12-28 19:24:24 +01:00