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Author SHA1 Message Date
Clifford Wolf
68304c6d17
Merge pull request #687 from trcwm/master 
Liberty file: error when it contains pin references to non-existing pins
 2018-11-04 10:08:33 +01:00
Clifford Wolf
18a4c1cdac
Merge pull request #688 from ZipCPU/rosenfell 
Make rose and fell dependent upon LSB only
 2018-11-04 10:04:48 +01:00
ZipCPU
39f891aebc Make and dependent upon LSB only 2018-11-03 13:39:32 -04:00
Niels Moseley
04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley
d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
Clifford Wolf
d86ea6badd Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 15:25:24 +01:00
Clifford Wolf
b6781c6f4b Add support for signed $shift/$shiftx in smt2 back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 11:40:58 +01:00
Clifford Wolf
b4d82aa245 Merge branch 'igloo2' 2018-10-31 15:37:39 +01:00
Clifford Wolf
d084fb4c3f Fix sf2 LUT interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:36:53 +01:00
Clifford Wolf
cf79fd4376 Basic SmartFusion2 and IGLOO2 synthesis support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:28:57 +01:00
Clifford Wolf
82965d60f5
Merge pull request #680 from jburgess777/fix-empty-string-back-assert 
Avoid assert when label is an empty string
 2018-10-30 11:25:07 +01:00
Jon Burgess
6732e56632 Avoid assert when label is an empty string 
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
 2018-10-28 14:57:04 +00:00
Benedikt Tutzer
5c59429893 added all variable in __init__.py to allow importing of the whole module 2018-10-25 16:32:28 +02:00
Benedikt Tutzer
0b81629779 changed dlopen flags to support plugins 2018-10-25 16:19:22 +02:00
Benedikt Tutzer
e7880bab20 removed debug output from make 2018-10-25 15:06:55 +02:00
Benedikt Tutzer
a13cba31c9 removed deletes 2018-10-25 15:06:26 +02:00
Clifford Wolf
db676957a0
Merge pull request #678 from whentze/master 
Fix unhandled std::out_of_range in run_frontend() due to integer underflow
 2018-10-25 13:23:26 +02:00
Clifford Wolf
5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Benedikt Tutzer
05a9adfdeb added py_wrap_generator 2018-10-25 12:27:56 +02:00
Udi Finkelstein
536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf
7703be045a
Merge pull request #677 from daveshah1/ecp5_dsp 
ecp5: Add blackboxes for MULT18X18D and ALU54B
 2018-10-23 19:18:45 +02:00
whentze
9ed77f5ba8 fix unhandled std::out_of_range when calling yosys with 3-character argument 2018-10-22 19:40:22 +02:00
David Shah
b65932edc4 ecp5: Remove DSP parameters that don't work 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 16:20:38 +01:00
rafaeltp
f8b97e21f3 using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal 2018-10-21 11:32:44 -07:00
David Shah
101f5234ff ecp5: Add DSP blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 19:27:02 +01:00
rafaeltp
7b964bfb83 cleaning up for PR 2018-10-20 18:02:59 -07:00
rafaeltp
ce069830c5 fixing code style 2018-10-20 17:57:26 -07:00
rafaeltp
0ad4321781 solves #675 2018-10-20 17:50:21 -07:00
rafaeltp
f25d0de6f8
Merge pull request #1 from YosysHQ/master 
updating
 2018-10-20 17:01:09 -07:00
Clifford Wolf
23b69ca32b Improve read_verilog range out of bounds warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-20 23:48:53 +02:00
Clifford Wolf
f3de732fb4
Merge pull request #674 from rubund/feature/svinterface_at_top 
Support for SystemVerilog interfaces as ports in the top level module + test case
 2018-10-20 23:28:09 +02:00
Ruben Undheim
436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim
d9a4381012 Fixed memory leak 2018-10-20 11:57:39 +02:00
Clifford Wolf
11c8a9eb96
Merge pull request #673 from daveshah1/ecp5_improve 
Small ECP5 improvements
 2018-10-19 17:32:42 +02:00
David Shah
d29b517fef ecp5: Sim model fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
David Shah
677b8ed3ca ecp5: Add latch inference 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 15:16:40 +01:00
Clifford Wolf
6514443a5c
Merge pull request #672 from daveshah1/fix_bram 
memory_bram: Reset make_outreg when growing read ports
 2018-10-19 16:09:11 +02:00
David Shah
3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Clifford Wolf
2e32d05eab
Merge pull request #671 from rafaeltp/master 
adding offset info to memories on verilog output
 2018-10-19 13:05:51 +02:00
Clifford Wolf
2a104b29fd
Merge pull request #670 from rubund/feature/basic_svinterface_test 
Basic test for checking correct synthesis of SystemVerilog interfaces
 2018-10-19 13:03:38 +02:00
rafaeltp
c7770d9eea adding offset info to memories 2018-10-18 16:22:33 -07:00
rafaeltp
609f46eeb7 adding offset info to memories 2018-10-18 16:20:21 -07:00
Ruben Undheim
d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00
Clifford Wolf
a25f370191 Update ABC to git rev 14d985a 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-18 12:26:53 +02:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Clifford Wolf
24a5c65856
Merge pull request #657 from mithro/xilinx-vpr 
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
 2018-10-18 10:54:03 +02:00
Clifford Wolf
93d99559ef
Merge pull request #664 from tklam/ignore-verilog-protect 
Ignore protect endprotect
 2018-10-18 10:52:07 +02:00
Clifford Wolf
22d9535a24 Update ABC to git rev c5b48bb 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-17 12:23:50 +02:00