373 commits

Author	SHA1	Message	Date
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	0c4c79c4c6	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	2014-06-16 15:02:40 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	5281562d0e	made the generate..endgenrate keywords optional	2014-06-06 23:05:01 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	f9c1cd5edb	Improved error message for options after front-end filename arguments	2014-06-04 09:10:50 +02:00
Clifford Wolf	7188542155	Fixed clang -Wdeprecated-register warnings	2014-04-20 14:28:23 +02:00
Clifford Wolf	a1be4816d6	Replaced depricated %name-prefix= bison directive	2014-04-20 14:22:11 +02:00
Clifford Wolf	fad8558eb5	Merged OSX fixes from Siesh1oo with some modifications	2014-03-13 12:48:10 +01:00
Clifford Wolf	9992026a8d	Added support for `line compiler directive	2014-03-11 14:06:57 +01:00
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	7d7e068dd1	Added a warning note about error reporting to read_verilog help message	2014-02-16 20:20:25 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	007bdff55d	Added support for functions returning integer	2014-02-12 23:29:54 +01:00
Clifford Wolf	aa8e754ae5	Added read_verilog -setattr	2014-02-05 11:22:10 +01:00
Clifford Wolf	cdd6e11af5	Added support for blanks after -I and -D in read_verilog	2014-02-02 13:06:21 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	13359d65ba	Fixed parsing of verilog macros at end of line	2014-01-18 19:22:20 +01:00
Clifford Wolf	6170cfe9cd	Added verilog_defaults command	2014-01-17 17:22:29 +01:00
Clifford Wolf	1dcbba1abf	Fixed parsing of non-arg macro calls followed by "("	2013-12-27 16:25:27 +01:00
Clifford Wolf	72026a934e	Fixed parsing of macros with no arguments and expansion text starting with "("	2013-12-27 15:05:52 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	507c63d112	Added support for local regs in named blocks	2013-12-04 09:10:16 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys|synthesis) comment support	2013-11-20 11:44:09 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	e340532ce5	Added init= attribute for fpga-style reset values	2013-11-20 01:49:37 +01:00
Clifford Wolf	0dfdbd991a	Fixed parsing of module arguments when one type is used for many args	2013-11-19 20:35:31 +01:00
Clifford Wolf	63060dcd2e	Fixed parsing of "parameter integer"	2013-11-13 15:30:23 +01:00
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Johann Glaser	f352205635	fixed Verilog parser filename and line numbering issue with include files	2013-08-21 09:20:59 +02:00