205 commits

Author	SHA1	Message	Date
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	ae02d9cb9a	Fixed $memwr/$memrd order in memory_dff	2014-09-16 12:40:58 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	6ff46323a3	Improved write address decoder generation memory_map	2014-08-30 18:18:15 +02:00
Clifford Wolf	66763fad4e	Using worker class in memory_map	2014-08-30 17:39:08 +02:00
Clifford Wolf	b4f10e342c	Various improvements in memory_dff pass	2014-08-06 14:31:38 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	d13eb7e099	Added ModIndex helper class, some changes to RTLIL::Monitor	2014-08-01 17:14:32 +02:00
Clifford Wolf	32a1cc3efd	Renamed modwalker.h to modtools.h	2014-07-31 23:30:18 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	49f72421d5	Using new obj iterator API in a few places	2014-07-27 11:32:42 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	4e802eb7f6	Fixed all users of SigSpec::chunks_rw() and removed it	2014-07-23 15:36:09 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	a8d3a68971	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	2014-07-23 09:49:43 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	efd9604dfb	Improved memory_share log messages	2014-07-19 15:46:11 +02:00
Clifford Wolf	e0a819dbe5	More verbose memory_share help message	2014-07-19 15:34:14 +02:00
Clifford Wolf	297a0962ea	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
Clifford Wolf	26f982ac0b	Fixed bug in memory_share feedback-to-en code	2014-07-19 15:32:14 +02:00
Clifford Wolf	e441f07d89	Added translation from read-feedback to en-signals in memory_share	2014-07-18 16:46:40 +02:00
Clifford Wolf	a341931972	Only create collision detect logic in memory_share if necessary	2014-07-18 14:32:40 +02:00
Clifford Wolf	ab4b26679f	Added memory_share	2014-07-18 13:16:56 +02:00
Clifford Wolf	765f172211	Changes to "memory" pass for new $memwr/$mem WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	68c99bf734	Fixed log messages in memory_dff	2014-06-01 11:32:27 +02:00
Clifford Wolf	7f52c18a22	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	2014-02-08 19:13:19 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	67b0ce2578	Only generate write-enable $and if WE is not constant 1 in memory_map	2014-02-02 21:27:26 +01:00
Clifford Wolf	f3154f5694	Added automatic memid generation to memory_unpack command	2014-01-17 00:15:15 +01:00
Clifford Wolf	4d8318ad1b	Added memory_unpack command	2014-01-17 00:05:02 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	97efc2ed5f	A fix in memory_dff for write ports with static addresses	2013-12-01 14:08:18 +01:00