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Author	SHA1	Message	Date
Yosys Bot	699a98b265	Bump version	2021-01-21 00:10:05 +00:00
Claire Xen	b734f2c932	Merge pull request #2552 from YosysHQ/claire/yosyshq ... Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific	2021-01-21 00:54:45 +01:00
Claire Xenia Wolf	acad7a6e40	Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>	2021-01-20 20:48:10 +01:00
Miodrag Milanović	bfa353f154	Merge pull request #2536 from TobiasFaller/master ... Fixed missing goto statement in passes/techmap/abc.cc	2021-01-20 20:42:02 +01:00
Miodrag Milanović	00f02e0589	Merge pull request #2551 from zachjs/wire-logic ... sv: fix support wire and var data type modifiers	2021-01-20 18:31:49 +01:00
Zachary Snow	006c18fc11	sv: fix support wire and var data type modifiers	2021-01-20 09:16:21 -07:00
Zachary Snow	4fadcc8f25	verilog: allow spaces in macro arguments	2021-01-20 08:49:58 -07:00
Yosys Bot	4762cc06c6	Bump version	2021-01-19 00:10:05 +00:00
Peter Gadfort	169234d6e9	adding support for passing multiple liberty files to abc	2021-01-18 16:47:49 -05:00
whitequark	e991ceeef3	Merge pull request #2547 from zachjs/plugin-so-dsym ... Add plugin.so.dSYM to .gitignore	2021-01-18 20:21:20 +00:00
whitequark	056c12eb6f	Merge pull request #2312 from antmicro/typedef-inout ... Add support for user types in IOs	2021-01-18 20:20:52 +00:00
Zachary Snow	4c108b4419	Add plugin.so.dSYM to .gitignore ... This artifact is automatically generated by the builtin clang on macOS when -g is used.	2021-01-18 11:13:21 -07:00
Kamil Rakoczy	d69ddf19da	Add typedef input/output test ... Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>	2021-01-18 17:31:22 +01:00
Kamil Rakoczy	61501e3266	Fix input/output attributes when resolving typedef of wire ... Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>	2021-01-18 17:31:22 +01:00
Lukasz Dalek	09071afe15	Parse package user type in module port list ... Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>	2021-01-18 17:31:22 +01:00
Iris Johnson	c8415884d1	Improves the previous commit with a more complete coverage of the cases	2021-01-15 13:59:20 -06:00
Yosys Bot	339848b954	Bump version	2021-01-15 00:10:05 +00:00
Iris Johnson	86607d0fdc	Handle sliced bits as clock inputs (fixes #2542)	2021-01-14 16:36:21 -06:00
Marcelina Kościelnicka	01626e6746	opt_share: Fix X and CO signal width for shifted $alu in opt_share. ... These need to be the same length as actual Y, not visible part of Y. Fixes #2538.	2021-01-14 14:54:08 +01:00
Yosys Bot	7cd044bbc4	Bump version	2021-01-14 00:10:05 +00:00
Claire Xen	0927675147	Merge pull request #2537 from pepijndevos/spice ... Add buffer option to spice backend	2021-01-13 19:08:25 +01:00
Pepijn de Vos	e789a00557	add buffer option to spice backend	2021-01-13 17:24:28 +01:00
Tobias Faller	760a2c1343	Fixed missing goto statement in passes/techmap/abc.cc	2021-01-12 16:17:51 +01:00
Yosys Bot	b0004911ca	Bump version	2021-01-05 00:10:05 +00:00
whitequark	b00e55a16a	Merge pull request #2522 from tomverbeure/simlib_typos2 ... Fix some trivial typos.	2021-01-04 14:04:17 +00:00
Xiangyu Xu	c4e23aab55	Add boost-python3 ... If enable python-api, do need boost-python3.	2021-01-04 03:23:09 -06:00
Tom Verbeure	3a8eecebba	Fix indents.	2021-01-04 00:17:16 -08:00
Tom Verbeure	bb3439562e	Add -nosynthesis flag for read_verilog command.	2021-01-04 00:11:01 -08:00
Tom Verbeure	87637e8359	Fix some trivial typos.	2021-01-03 23:52:59 -08:00
Yosys Bot	b72c294653	Bump version	2021-01-02 00:10:04 +00:00
whitequark	b0d4c63957	Merge pull request #2480 from YosysHQ/dave/nexus-lram ... nexus: Add LRAM inference	2021-01-01 09:49:00 +00:00
whitequark	1387c3b41d	Merge pull request #2512 from umarcor/plugin-err ... plugin: enhance no-plugin error	2021-01-01 09:39:17 +00:00
whitequark	8759ed9883	Merge pull request #2515 from umarcor/fix/ghdl ... makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX	2021-01-01 09:37:12 +00:00
whitequark	bc2de4567c	Merge pull request #2518 from zachjs/recursion ... verilog: improved support for recursive functions	2021-01-01 09:32:26 +00:00
whitequark	1a80194cd3	Merge pull request #2517 from zachjs/sv-tf-implied-direction ... sv: complete support for implied task/function port directions	2021-01-01 09:31:49 +00:00
Zachary Snow	2085d9a55d	verilog: improved support for recursive functions	2020-12-31 18:33:59 -07:00
Zachary Snow	75abd90829	sv: complete support for implied task/function port directions	2020-12-31 16:17:13 -07:00
umarcor	7f28afd3ac	makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX	2020-12-30 07:06:52 +01:00
Yosys Bot	48d0aeb094	Bump version	2020-12-30 00:10:06 +00:00
umarcor	e61b107072	plugin: enhance no-plugin error	2020-12-29 05:50:04 +01:00
whitequark	da1d06d785	Merge pull request #2509 from zachjs/issue-2427 ... Fix elaboration of whole memory words used as indices	2020-12-29 02:59:09 +00:00
whitequark	e609bc4898	Merge pull request #2514 from umarcor/feat/ghdl ... makefile: add support for built-in ghdl-yosys-plugin	2020-12-29 02:58:41 +00:00
Yosys Bot	0347b441a1	Bump version	2020-12-29 00:10:04 +00:00
umarcor	a652430c71	makefile: add support for built-in ghdl-yosys-plugin ... Co-authored-by: Tristan Gingold <tgingold@free.fr> Co-authored-by: whitequark <whitequark@whitequark.org>	2020-12-28 22:45:00 +01:00
whitequark	c718780ff6	Merge pull request #2511 from umarcor/feat/msys2-32 ... Update MSYS2 build system	2020-12-28 02:33:58 +00:00
whitequark	f4a800899c	Merge pull request #2507 from umarcor/fix/msys2 ... kernel/yosys.h: undef CONST on WIN32	2020-12-28 02:33:30 +00:00
umarcor	0ebce301c1	makefile: rename msys2 to msys2-32, config PREFIX	2020-12-28 02:23:04 +01:00
umarcor	16c4182c74	kernel/yosys.h: undef CONST on WIN32	2020-12-28 02:21:19 +01:00
Yosys Bot	f48298347c	Bump version	2020-12-28 00:10:04 +00:00
Claire Xen	d30063ea65	Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast ... CODEOWNERS: add @zachjs as Verilog/AST frontend owner	2020-12-27 16:33:58 +01:00