mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity
5336 commits 122 branches 59 tags 72 MiB
Commit graph

5336 commits

This branch
This branch
All branches
Author SHA1 Message Date
David Shah
bdfead8c64 ecp5: Adding BRAM maps for all size options 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 17:18:17 +01:00
David Shah
983fb7ff88 ecp5: First BRAM type maps successfully 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:35:19 +01:00
David Shah
2ef1af8b58 ecp5: Script for BRAM IO connections 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-10 16:11:00 +01:00
David Shah
346cbbdbdc ecp5: Adding BRAM initialisation and config 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-09 14:19:04 +01:00
Tim 'mithro' Ansell
b111ea1228 xilinx: Still map LUT7/LUT8 to Xilinx specific primitives. 
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
 2018-10-08 16:52:12 -07:00
Clifford Wolf
3bb9288d65 Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8e13f2913d Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
05e1c39064 Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
3661c27acd Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-08 11:38:10 -07:00
Adrian Wheeldon
81d77c4911 Fix IdString M in setup_stdcells() 2018-10-08 11:38:10 -07:00
Clifford Wolf
ea82191c57 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
cd261795ba xilinx: Adding missing inout IO port to IOBUF 2018-10-08 11:38:10 -07:00
Tom Verbeure
b8950bd603 Fix for issue 594. 2018-10-08 11:38:10 -07:00
Dan Gisselquist
d3be61b9dc Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
David Shah
ae8637cd63 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
7d88d851d8 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
b3de38d357 Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
89ef6600bc Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
e8431d1508 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
a9085ff4af Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
6cf9fca93b added prefix to FDirection constants, fixing windows build 2018-10-08 11:38:10 -07:00
Clifford Wolf
f73e7116f9 Update CHANGLELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8340d44986 Update Changelog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
24951ddc77 Fix Cygwin build and document needed packages 2018-10-08 11:38:10 -07:00
acw1251
33ac82a5fe Fixed typo in "verilog_write" help message 2018-10-08 11:38:10 -07:00
Clifford Wolf
9850de405a Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-07 19:48:55 +02:00
David Shah
31e22c8b96 ecp5: Add blackbox for DP16KD 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-05 11:35:59 +01:00
Clifford Wolf
ed1f0b2577
Merge pull request #651 from ARandomOWL/stdcells_fix 
Fix IdString M in setup_stdcells()
 2018-10-05 09:59:57 +02:00
Clifford Wolf
115ca57647 Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:41:30 +02:00
Clifford Wolf
257a846113
Merge pull request #654 from mithro/patch-1 
Fix misspelling in issue_template.md
 2018-10-05 09:29:26 +02:00
Clifford Wolf
4b0448fc2c Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-05 09:26:10 +02:00
Tim Ansell
63d53006cb
Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-04 17:15:30 -07:00
Adrian Wheeldon
1355492c89 Fix IdString M in setup_stdcells() 2018-10-04 15:36:26 +01:00
Clifford Wolf
5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Clifford Wolf
bed6c26a6e
Merge pull request #650 from mithro/patch-1 
xilinx: Adding missing inout IO port to IOBUF
 2018-10-04 11:30:00 +02:00
Tim Ansell
ad975fb694
xilinx: Adding missing inout IO port to IOBUF 2018-10-03 16:38:32 -07:00
tklam
27c46d94e3 Merge branch 'master' of https://github.com/YosysHQ/yosys 2018-10-03 21:17:03 +08:00
Clifford Wolf
76baae4b94
Merge pull request #645 from daveshah1/ecp5_dram_fix 
ecp5: Don't map ROMs to DRAM
 2018-10-02 10:00:10 +02:00
Clifford Wolf
0a7751a11b
Merge pull request #646 from tomverbeure/issue594 
Fix for issue 594.
 2018-10-02 09:51:44 +02:00
Tom Verbeure
cb214fc01d Fix for issue 594. 2018-10-02 07:44:23 +00:00
Aman Goel
90e0938f9a Update to .smv backend 
Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
 2018-10-01 19:03:10 -04:00
Dan Gisselquist
62424ef3de Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-01 19:41:35 +02:00
David Shah
fcd39e1398 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-01 18:34:41 +01:00
Aman Goel
33cb5e05be
Merge pull request #4 from YosysHQ/master 
Merge with official repo
 2018-10-01 09:09:40 -04:00
Clifford Wolf
4d2917447c Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-30 18:44:07 +02:00
Clifford Wolf
9f9fe94b35 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-30 18:43:35 +02:00
Clifford Wolf
ac4000d855 Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-28 17:20:43 +02:00
Clifford Wolf
031824e38c Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-28 17:20:16 +02:00
tklam
b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam
2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00