664 commits

Author	SHA1	Message	Date
Clifford Wolf	e07698818d	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data	2014-09-01 11:36:02 +02:00
Clifford Wolf	2a1b08aeb3	Added design->scratchpad	2014-08-30 19:37:12 +02:00
Clifford Wolf	7bbbe3580d	Optimize shift ops with constant rhs in opt_const	2014-08-24 17:08:43 +02:00
Clifford Wolf	641501203c	Added some additional log messages to opt_const	2014-08-24 17:08:43 +02:00
Clifford Wolf	410d043dd8	Renamed toposort.h to utils.h	2014-08-17 00:55:35 +02:00
Clifford Wolf	eb17fbade5	Added "opt -fast"	2014-08-16 15:34:15 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	8fd1c269ac	Fixed a performance bug in opt_reduce	2014-08-02 15:12:16 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	bd74ed7da4	Replaced sha1 implementation	2014-08-01 19:01:10 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	0c86d6106c	Added SigPool::check(bit)	2014-07-27 15:38:02 +02:00
Clifford Wolf	77a1462f2d	Fixed bug in opt_clean	2014-07-27 15:13:29 +02:00
Clifford Wolf	d07a871d35	Improved performance of opt_const on large modules	2014-07-27 14:50:25 +02:00
Clifford Wolf	dbb3556e3f	Fixed a bug in opt_clean and some RTLIL API usage cleanups	2014-07-27 13:19:05 +02:00
Clifford Wolf	49f72421d5	Using new obj iterator API in a few places	2014-07-27 11:32:42 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	3f4e3ca8ad	More RTLIL::Cell API usage cleanups	2014-07-26 16:14:02 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	0520bfea89	Fixed memory corruption in "opt_reduce" pass	2014-07-25 12:49:51 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	9962384d3e	Added cover() calls to opt_const	2014-07-24 20:47:18 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	a62c21c9c6	Removed RTLIL::SigSpec::expand() method	2014-07-23 19:34:51 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	a8d3a68971	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	2014-07-23 09:49:43 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	137dbf3cf7	Added "opt_const -keepdc"	2014-07-21 21:38:55 +02:00
Clifford Wolf	1873480ca5	Added mul to mux conversion to "opt_const -fine"	2014-07-21 17:19:50 +02:00
Clifford Wolf	1241a9fd50	Added "opt_const -fine" and "opt_reduce -fine"	2014-07-21 16:34:16 +02:00
Clifford Wolf	e035f1d886	Added opt_const support for simple identities	2014-07-21 14:41:02 +02:00
Clifford Wolf	309ae98246	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	2014-07-18 10:28:45 +02:00
Clifford Wolf	1b00861d0a	Improved opt_reduce handling of mem wr_en mux bits	2014-07-17 12:12:04 +02:00
Clifford Wolf	d678b6533d	improved opt_reduce for $mem/$memwr WR_EN multiplexers	2014-07-16 14:08:51 +02:00
Clifford Wolf	68c059565a	Fixed bug in opt_reduce (see vloghammer issue_044)	2014-05-12 12:45:47 +02:00
Clifford Wolf	9a34486bfb	Fixed performance problem in opt_mux with nets driven by many conflicting drivers	2014-03-19 10:05:01 +01:00
Clifford Wolf	9b9c3327cc	Fixed undef handling in opt_reduce	2014-03-06 14:18:34 +01:00