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Author SHA1 Message Date
Marcelina Kościelnicka
f3f55ae7c2 dfflegalize: Prefer mapping dff to sdff before adff 
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
 2020-07-05 12:01:43 +02:00
Marcelina Kościelnicka
7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Dan Ravensloft
b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka
1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
Marcelina Kościelnicka
9beed4d771 gowin: Fix INIT values in sim library. 2020-07-05 03:03:48 +02:00
Dan Ravensloft
01772dec8c gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
Marcelina Kościelnicka
3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Dan Ravensloft
7d5828a706 Add option to use ccache when building 2020-07-04 19:59:39 +01:00
Marcelina Kościelnicka
6b0ac04698 efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
Dan Ravensloft
c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung
52fbaeca07 tests: update fsm.ys resource count 
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
 2020-07-04 19:45:10 +02:00
Eddie Hung
27a9d1b6e6 abc9: only techmap (* abc9_flop *) modules 2020-07-04 19:45:10 +02:00
Eddie Hung
2bdced0d68 intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF 2020-07-04 19:45:10 +02:00
Eddie Hung
0ba79feb6f abc9: techmap from user design to allow abc9_flop modules to be composed 
from other primitives
 2020-07-04 19:45:10 +02:00
Eddie Hung
3db3e1e149 intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY 2020-07-04 19:45:10 +02:00
Dan Ravensloft
83cde2d02b intel_alm: ABC9 sequential optimisations 2020-07-04 19:45:10 +02:00
Rupert Swarbrick
a9b61080a4 Add newlines to help text for dfflegalize 
I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:

passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
  114 |   log("");
      |       ^~

(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).
 2020-07-03 12:30:12 +02:00
clairexen
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial 
verific: rewrite initial assume/asserts prior to elaboration
 2020-07-02 17:50:22 +02:00
clairexen
e4b9e64d1b
Merge pull request #2208 from boqwxp/qbfsat-cleanup 
qbfsat: Cleanup and refactoring
 2020-07-02 17:48:37 +02:00
clairexen
5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize 
Add dfflegalize pass.
 2020-07-02 17:46:11 +02:00
clairexen
d3422f8a5e
Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff 
fmcombine: use the master ff cell type list
 2020-07-02 17:43:48 +02:00
clairexen
5dbf91847a
Merge pull request #2210 from YosysHQ/mwk/fix-opt_merge 
opt_merge: use the master FF type list
 2020-07-02 17:43:34 +02:00
clairexen
5d740ec4b4
Merge pull request #2195 from YosysHQ/mwk/manual-gates 
Add a few more gate types to the manual.
 2020-07-02 17:43:10 +02:00
Alberto Gonzalez
56f98b9e3d
qbfsat: Remove useless comment and #ifndef guards. 2020-07-01 19:55:16 +00:00
Alberto Gonzalez
3345d39e6f
qbfsat: Specify default values for some options in the help message. 2020-07-01 19:55:16 +00:00
Alberto Gonzalez
95e8016811
qbfsat: Clean up external executable command lines and update temporary directory name. 2020-07-01 19:55:16 +00:00
Alberto Gonzalez
8cd60be654
qbfsat: Clean up and refactor data structures into qbfsat.h. 2020-07-01 19:55:16 +00:00
clairexen
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen
8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
clairexen
b1707407a0
Merge pull request #2138 from boqwxp/qbfsat-oflag 
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC
 2020-07-01 16:35:27 +02:00
clairexen
2b0f6e24e2
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization 
qbfsat: Fix name-based hole specialization
 2020-07-01 16:34:32 +02:00
Marcelina Kościelnicka
6b42819a37 dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
e3564b4502 Add dfflegalize pass. 2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
7c91f13f51 fmcombine: use the master ff cell type list 2020-06-30 21:07:17 +02:00
Marcelina Kościelnicka
77b15dd8e9 opt_merge: use the master FF type list 2020-06-30 20:57:35 +02:00
clairexen
9d658a1970
Merge pull request #2136 from zachjs/master 
Allow constant function calls in for loops and generate if and case
 2020-06-30 17:38:49 +02:00
clairexen
3fb5b4fd8a
Merge pull request #2199 from YosysHQ/mmicko/sim_memory 
sim - error when memrd and memwr detected
 2020-06-30 17:12:51 +02:00
clairexen
275cee71f6
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang 
Use ID macro to fix assertion
 2020-06-30 17:11:13 +02:00
clairexen
79d81b7f4f
Merge pull request #2209 from YosysHQ/verific_update 
Update verific API version check
 2020-06-30 17:05:51 +02:00
Marcelina Kościelnicka
817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Miodrag Milanovic
561890c4e8 Update verific API version check 2020-06-30 12:13:13 +02:00
Alberto Gonzalez
83c595aaac
qbfsat: Add -O[012] options to control pre-solving simplification with ABC. 
Thanks to @mwk for the gate mapping part of the ABC scripts.

Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
 2020-06-30 06:44:17 +00:00
Alberto Gonzalez
f544a2cc84
qbfsat: Fix name-based hole specialization. 
Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.
 2020-06-30 01:53:21 +00:00
whitequark
f7fdd99e45
Merge pull request #2205 from whitequark/fix-2204 
techmap: don't drop attributes on replaced cells
 2020-06-30 00:08:08 +00:00
whitequark
a97c13f0ca techmap: don't drop attributes on replaced cells. 
This was introduced in 76c4ee4ea5.

Fixes #2204.
 2020-06-29 23:14:13 +00:00
Zachary Snow
27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Miodrag Milanović
4160acc0b1
Merge pull request #2200 from YosysHQ/mmicko/fix_expose 
expose pass fix
 2020-06-29 15:16:29 +02:00
Miodrag Milanovic
405b4e97a1 Give error that options are exclusive 2020-06-29 14:45:49 +02:00
Miodrag Milanovic
0545a042f3 cleanup 2020-06-29 14:42:48 +02:00
whitequark
7860fb628f
Merge pull request #2197 from Xiretza/test_cell-shifts 
test_cell: don't generate directional shifts with \B_SIGNED=1
 2020-06-29 12:34:09 +00:00