mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
5327 commits 124 branches 59 tags 44 MiB
Commit graph

5327 commits

This branch
This branch
All branches
Author SHA1 Message Date
Clifford Wolf
49859393bb Improved attributes API and handling of "src" attributes 2015-04-24 22:04:05 +02:00
Clifford Wolf
687f5a5b12 iCE40 bram progress 2015-04-24 15:38:11 +02:00
Clifford Wolf
308a59aa18 iCE40 bram tests and fixes 2015-04-24 08:32:07 +02:00
Clifford Wolf
d6f7698f59 Added ice40 bram support 2015-04-24 00:06:50 +02:00
Clifford Wolf
11f77205f5 Fixed memory_share for unconditional write with part select to memory 2015-04-22 06:40:23 +02:00
Clifford Wolf
1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models 2015-04-19 21:37:40 +02:00
Clifford Wolf
7ff802e199 Verilog front-end: define `BLACKBOX in -lib mode 2015-04-19 21:30:46 +02:00
Clifford Wolf
49ef830464 added sync reset to ice40 test_ffs.sh 2015-04-18 09:41:31 +02:00
Clifford Wolf
f564a65851 Added ice40 test_arith 2015-04-18 09:33:34 +02:00
Clifford Wolf
f78fa718be Added ice40 SB_CARRY support 2015-04-18 09:33:08 +02:00
Clifford Wolf
faa95dd845 don't consider blackbox modules in "sat" command 2015-04-18 09:29:03 +02:00
Clifford Wolf
9041f34233 Improved handling of init values in opt_rmdff 
based on a patch by Mingyu Gao, user gaomy3832 on github
 2015-04-18 08:04:31 +02:00
Clifford Wolf
8cdbcf6859 Bugfix for $_DFF_?_ in "dff2dffe -direct-match" 2015-04-17 21:35:59 +02:00
Clifford Wolf
661b647559 Added mapping of synchronous set/reset to iCE40 flow 2015-04-17 11:54:25 +02:00
Clifford Wolf
e050467b89 Improved "maccmap" help message 2015-04-16 18:23:43 +02:00
Clifford Wolf
cfdc9fc50e A "#" does start a comment, not a label. 2015-04-16 18:13:41 +02:00
Clifford Wolf
31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name 2015-04-16 12:09:14 +02:00
Clifford Wolf
dc30b034f7 Fixed "dff2dffe -direct-match" 2015-04-16 11:47:59 +02:00
Clifford Wolf
3e9e6e1c22 Added simple ice40 dff tests 2015-04-16 11:31:15 +02:00
Clifford Wolf
0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf
f80d020f17 Added "dff2dffe -direct-match" 2015-04-16 11:30:17 +02:00
Clifford Wolf
4529c56cc6 use "hierarchy -auto-top" in synth_ice40 2015-04-14 13:45:15 +02:00
Clifford Wolf
06ce496f8d more cells in ice40 cell library 2015-04-14 13:44:43 +02:00
Clifford Wolf
2fc2f8f5b3 Added "splice -wires" 2015-04-13 19:28:12 +02:00
Clifford Wolf
e305d85807 Added handling of bool-output cells to "wreduce" 2015-04-13 19:27:49 +02:00
Clifford Wolf
3481f46d1e Improved xilinx "bram1" test 2015-04-09 17:12:12 +02:00
Clifford Wolf
7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf
44519d4399 Added back-end auto-detect for .edif and .json 2015-04-09 15:37:54 +02:00
Clifford Wolf
d176e613c2 Minor fixes in handling of "init" attribute 2015-04-09 15:12:26 +02:00
Clifford Wolf
229825e1b8 Xilinx DRAMS: RAM64X1D, RAM128X1D 2015-04-09 13:37:07 +02:00
Clifford Wolf
25781e329b Fixed const2big performance bug 2015-04-09 13:20:19 +02:00
Clifford Wolf
be7b9b34ca techmap code cleanup 2015-04-09 12:02:26 +02:00
Clifford Wolf
b00cad81d7 Towards DRAM support in Xilinx flow 2015-04-09 08:17:14 +02:00
Clifford Wolf
21a1cc1b60 Added support for "file names with blanks" 2015-04-08 12:14:34 +02:00
Clifford Wolf
aa0ab975b9 Removed "techmap -share_map" (use "-map +/filename" instead) 2015-04-08 12:13:53 +02:00
Clifford Wolf
8eadd8fb18 Added %M and %C select operators 2015-04-07 22:22:09 +02:00
Clifford Wolf
724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf
1f33b2a490 Added "chparam -list" 2015-04-07 19:21:30 +02:00
Clifford Wolf
590f74d8f0 Added decoder generation to "muxcover" 2015-04-07 18:03:27 +02:00
Clifford Wolf
aae5f2ca08 Added hashlib support for std::tuple<> 2015-04-07 17:23:30 +02:00
Clifford Wolf
f7fb21f185 Added "muxcover" command 2015-04-07 15:42:25 +02:00
Clifford Wolf
b31e77fd06 Added pool<K>::pop() 2015-04-07 15:07:01 +02:00
Clifford Wolf
c1af590f4e typo fix 2015-04-07 07:43:01 +02:00
Clifford Wolf
329b841aac Added "chparam" command 2015-04-07 07:30:14 +02:00
Clifford Wolf
8520b7fbe0 Added support for initialized xilinx brams 2015-04-06 17:07:10 +02:00
Clifford Wolf
169d1c4711 Added support for initialized brams 2015-04-06 17:06:15 +02:00
Clifford Wolf
d19866615b Added Xilinx test case for initialized brams 2015-04-06 13:27:11 +02:00
Clifford Wolf
4389d9306e Added Xilinx bram black-box modules 2015-04-06 08:44:30 +02:00
Clifford Wolf
c0e2b3eb11 Added "port_directions" to write_json output 2015-04-06 01:49:58 +02:00
Clifford Wolf
a1c62b79d5 Avoid parameter values with size 0 ($mem cells) 2015-04-05 18:04:19 +02:00