Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
619f2414e5
clkbufmap to only check clkbuf_inhibit if no selection given
2019-08-23 11:14:42 -07:00
Eddie Hung
4d89c3f468
Review comment from @cliffordwolf
2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
36d94caec1
Remove shregmap -tech xilinx additions
2019-08-22 11:22:09 -07:00
Eddie Hung
fe61dcce8b
Grammar
2019-08-20 20:05:51 -07:00
Eddie Hung
193eae0c84
techmap -max_iter to apply to each module individually
2019-08-20 19:50:20 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
7e010834eb
Fix typo
2019-08-19 10:41:18 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
8915f496d9
Merge pull request #1300 from YosysHQ/eddie/cleanup2
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Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
2019-08-17 15:01:31 +02:00
Eddie Hung
5abe133323
Use ID()
2019-08-16 16:38:49 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Eddie Hung
6b51c154c6
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-16 13:38:47 -07:00
Clifford Wolf
958be89c47
Merge pull request #1302 from mmicko/dfflibmap_regression
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DFFLIBMAP pass regression fix
2019-08-16 14:26:58 +02:00
Miodrag Milanovic
72eacdb9f8
Regression in abc9
2019-08-16 13:21:11 +02:00
Miodrag Milanovic
bb79e050a5
Just needed IDs to be IdString
2019-08-16 11:50:34 +02:00
Clifford Wolf
bb37a20e8d
Add missing NMUX to "abc -g" handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 10:36:11 +02:00
Eddie Hung
eae5a6b12c
Use ID::keep more liberally too
2019-08-15 14:51:12 -07:00
Eddie Hung
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
Eddie Hung
02dead2e60
ID(\\.*) -> ID(.*)
2019-08-15 10:25:54 -07:00
Eddie Hung
78ba8b8574
Transform all "\\*" identifiers into ID()
2019-08-15 10:19:29 -07:00
Eddie Hung
9f98241010
Transform "$.*" to ID("$.*") in passes/techmap
2019-08-15 10:05:08 -07:00
Eddie Hung
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
Eddie Hung
1551e14d2d
AND with an inverted input, causes X{,N}OR output to be inverted too
2019-08-14 16:26:24 -07:00
Eddie Hung
1e47e81869
Revert "Only sort leaves on non-ANDNOT/ORNOT cells"
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This reverts commit 5ec5f6dec7
2019-08-14 15:23:25 -07:00
Eddie Hung
5ec5f6dec7
Only sort leaves on non-ANDNOT/ORNOT cells
2019-08-14 11:25:56 -07:00
Eddie Hung
0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
2019-08-14 10:40:53 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
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A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
e4a0971581
Since $_ANDNOT_ is not symmetric, do not sort leaves
2019-08-12 11:17:15 -07:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
6d0be8d206
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-09 19:17:59 +02:00
