41 commits

Author	SHA1	Message	Date
Clifford Wolf	ab2d8e5c8c	Added PRIM_DLATCHRS support to verific front-end	2015-11-24 12:16:19 +01:00
Clifford Wolf	415e0a1b90	Fixed performance bug in Verific importer	2015-11-16 12:38:56 +01:00
Clifford Wolf	b18f3a2974	Changes for Verific 3.16_484_32_151112	2015-11-12 19:28:14 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
Clifford Wolf	acf010d30d	Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions	2014-11-08 11:38:44 +01:00
William Speirs	31267a1ae8	Header changes so it will compile on VS	2014-10-17 11:41:36 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	593264e9ed	Fixed building verific bindings	2014-08-12 15:21:06 +02:00
Clifford Wolf	c6fd82c70b	Fixed build of verific bindings	2014-07-31 16:45:23 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	7661ded8dd	Fixed verific bindings for new RTLIL api	2014-07-27 12:00:28 +02:00
Clifford Wolf	1488bc0c4f	Updated verific build/test instructions	2014-07-25 12:16:03 +02:00
Clifford Wolf	375aa71dfe	Various fixes in Verific frontend for new RTLIL API	2014-07-23 21:35:01 +02:00
Clifford Wolf	a3b9692a68	Fixed mapping of Verific WIDE_DFFRS operator	2014-03-20 13:40:01 +01:00
Clifford Wolf	470c2455e4	Fixed mapping of Verific FADD primitive with unconnected outputs	2014-03-20 13:26:52 +01:00
Clifford Wolf	cdf1257565	Progress in Verific bindings	2014-03-17 14:43:16 +01:00
Clifford Wolf	0b0dcfda7d	Progress in Verific bindings	2014-03-17 02:43:53 +01:00
Clifford Wolf	a67cd2d4a2	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
Clifford Wolf	acda74c12c	Added support for memories to verific bindings	2014-03-16 17:05:05 +01:00
Clifford Wolf	7545510edc	Use Verific Net::{IsGnd,IsPwr} API in Verific bindings	2014-03-16 16:06:03 +01:00
Clifford Wolf	0ebee4c8e7	Progress in Verific bindings	2014-03-15 22:51:12 +01:00
Clifford Wolf	fc2c821407	Progress in Verific bindings	2014-03-15 15:31:54 +01:00
Clifford Wolf	1d00ad9d4d	Progress in Verific bindings	2014-03-15 14:36:11 +01:00
Clifford Wolf	e37d672ae7	Progress in Verific bindings	2014-03-14 16:40:25 +01:00
Clifford Wolf	0ac915a757	Progress in Verific bindings	2014-03-14 11:46:13 +01:00
Clifford Wolf	9a1accf692	Progress in Verific bindings	2014-03-13 18:21:00 +01:00
Clifford Wolf	6a53bc7b27	Copy Verific vdbs files to Yosys "share" data directory	2014-03-13 17:34:31 +01:00
Clifford Wolf	7a1ac11203	Added test_navre.ys for verific frontend	2014-03-13 13:12:06 +01:00
Clifford Wolf	5a15539c9b	Improved verific command (added support for some operators)	2014-03-10 12:06:57 +01:00
Clifford Wolf	c71791a1ff	Improvements in verific command	2014-03-10 03:03:08 +01:00
Clifford Wolf	8d06f9f2fe	Added "verific" command	2014-03-09 20:40:04 +01:00