228 commits

Author	SHA1	Message	Date
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	0b1ce63a19	Added support for repeat stmt in const functions	2014-06-07 10:47:53 +02:00
Clifford Wolf	7c8a7b2131	further improved const function support	2014-06-07 00:02:05 +02:00
Clifford Wolf	76da2fe172	improved const function support	2014-06-06 22:55:02 +02:00
Clifford Wolf	5c10d2ee36	fix functions with no block (but single statement, loop, etc.)	2014-06-06 21:29:23 +02:00
Clifford Wolf	ab54ce17c8	improved ast simplify of const functions	2014-06-06 17:40:45 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	09805ee9ec	Include id2ast pointers when dumping AST	2014-03-05 19:56:31 +01:00
Clifford Wolf	d6a01fe412	Fixed merging of compatible wire decls in AST frontend	2014-03-05 19:55:58 +01:00
Clifford Wolf	de7bd12004	Bugfix in recursive AST simplification	2014-03-05 19:45:33 +01:00
Clifford Wolf	ae5032af84	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	2014-02-26 21:32:19 +01:00
Clifford Wolf	6bc94b7eb2	Don't blow up constants unneccessarily in Verilog frontend	2014-02-24 12:41:25 +01:00
Clifford Wolf	f8c9143b2b	Fixed bug in generation of undefs for $memwr MUXes	2014-02-22 17:08:00 +01:00
Clifford Wolf	4bd25edcd4	Cleanups in handling of read_verilog -defer and -icells	2014-02-20 19:12:32 +01:00
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	7ac524e8e8	Improved support for constant functions	2014-02-16 13:16:38 +01:00
Clifford Wolf	5e39e6ece2	Correctly convert constants to RTLIL (fixed undef handling)	2014-02-15 15:42:10 +01:00
Clifford Wolf	45d2b6ffce	Be more conservative with new const-function code	2014-02-14 20:45:30 +01:00
Clifford Wolf	e8af3def7f	Added support for FOR loops in function calls in parameters	2014-02-14 20:33:22 +01:00
Clifford Wolf	534c1a5dd0	Created basic support for function calls in parameter values	2014-02-14 19:56:44 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	f4f230d7cc	Fixed gcc compiler warnings with release build	2014-02-06 22:49:14 +01:00
Clifford Wolf	d267bcde4e	Fixed bug in sequential sat proofs and improved handling of asserts	2014-02-04 12:46:16 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	88fbdd4916	Fixed algorithmic complexity of AST simplification of long expressions	2014-01-20 20:25:20 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	a3d94bf888	Fixed typo in frontends/ast/simplify.cc	2014-01-12 21:04:42 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	364f277afb	Fixed a stupid access after delete bug	2013-12-29 20:18:22 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	891e4b5b0d	Keep strings as strings in const ternary and concat	2013-12-05 13:26:17 +01:00
Clifford Wolf	e935bb6eda	Added const folding support for $signed and $unsigned	2013-12-05 13:09:41 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	853538d78b	Fixed generate-for (and disabled double warning for auto-wire)	2013-12-04 21:33:00 +01:00
Clifford Wolf	3c220e0b32	Added support for $clog2 system function	2013-12-04 21:19:54 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	507c63d112	Added support for local regs in named blocks	2013-12-04 09:10:16 +01:00
Clifford Wolf	10aa08dca1	Fixed temp net name generation in rtlil process generator for abbreviated name matching	2013-11-28 21:47:08 +01:00
Clifford Wolf	0e52f3fa01	Added "src" attribute to processes	2013-11-28 17:37:50 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00