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Author	SHA1	Message	Date
Krystine Sherwin	1248af1e02	Tests: Prefer single quotes for regex Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.	2025-10-06 14:22:33 +13:00
CORRADI Quentin	e7156c644d	Standard compliance for tests/verilog/block_labels.ys genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration. Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.	2023-05-21 16:38:14 -04:00
Kamil Rakoczy	98c4feb72f	Add check of begin/end labels for genblock Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>	2021-02-04 17:16:30 +01:00

Author

SHA1

Message

Date

Krystine Sherwin

1248af1e02

Tests: Prefer single quotes for regex

Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.

2025-10-06 14:22:33 +13:00

CORRADI Quentin

e7156c644d

Standard compliance for tests/verilog/block_labels.ys

genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration.
Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.

2023-05-21 16:38:14 -04:00

Kamil Rakoczy

98c4feb72f

Add check of begin/end labels for genblock

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

2021-02-04 17:16:30 +01:00

3 commits