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Author	SHA1	Message	Date
David Shah	7a6551de36	Merge pull request #891 from YosysHQ/xilinx_keep ... xilinx: Add keep attribute where appropriate	2019-03-22 14:28:29 +00:00
David Shah	46f6a60d58	xilinx: Add keep attribute where appropriate ... Signed-off-by: David Shah <dave@ds0.me>	2019-03-22 13:57:17 +00:00
Clifford Wolf	7cfd83c341	Trim init attributes when resizing FFs in "wreduce", fixes #887 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-22 11:42:19 +01:00
Eddie Hung	4cc6b3e942	Add '-nosrl' option to synth_xilinx	2019-03-21 15:04:44 -07:00
Clifford Wolf	638be461c3	Fix mem2reg handling of memories with upto data ports, fixes #888 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-21 22:21:17 +01:00
Clifford Wolf	da42f10765	Improve "read_verilog -dump_vlog[12]" handling of upto ranges ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-21 22:20:16 +01:00
Clifford Wolf	9b0e7af6d7	Improve read_verilog debug output capabilities ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-21 20:52:29 +01:00
Eddie Hung	5597270b9e	Opt	2019-03-21 10:20:27 -07:00
Eddie Hung	2b911e270b	Fix spacing	2019-03-20 12:28:39 -07:00
Eddie Hung	81c207fb9b	Fine tune cells_map.v	2019-03-20 10:55:14 -07:00
Eddie Hung	505e4c2d59	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	2019-03-19 21:58:05 -07:00
Eddie Hung	5445cd4d00	Add support for variable length Xilinx SRL > 128	2019-03-19 17:44:33 -07:00
Eddie Hung	ae2a625d05	Restore original synth_xilinx commands	2019-03-19 16:14:08 -07:00
Eddie Hung	9156e18f92	Fix spacing	2019-03-19 16:12:32 -07:00
Eddie Hung	4cd8f02973	shregmap -tech xilinx to delete $shiftx for var length SRL	2019-03-19 15:05:08 -07:00
Eddie Hung	f239cb821e	Fix INIT for variable length SRs that have been bumped up one	2019-03-19 14:54:43 -07:00
Eddie Hung	24553326dd	Merge remote-tracking branch 'origin/master' into xc7srl	2019-03-19 13:11:30 -07:00
Eddie Hung	0ea7eba5f1	Make output port a non chain user	2019-03-19 13:08:43 -07:00
Clifford Wolf	8c0740bcf7	Merge pull request #885 from YosysHQ/clifford/fix873 ... Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873	2019-03-19 20:31:53 +01:00
Clifford Wolf	fe1fb1336b	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-19 20:30:28 +01:00
Eddie Hung	a7ac8393d4	Merge pull request #808 from eddiehung/read_aiger ... Add new read_aiger frontend	2019-03-19 09:41:40 -07:00
Eddie Hung	02e8dc7ad2	Merge https://github.com/YosysHQ/yosys into read_aiger	2019-03-19 08:52:31 -07:00
Eddie Hung	3e89cf68bd	Add author name	2019-03-19 08:52:06 -07:00
Clifford Wolf	61f37706f9	Merge pull request #884 from zachjs/master ... fix local name resolution in prefix constructs	2019-03-19 14:08:57 +01:00
Zachary Snow	a5f4b83637	fix local name resolution in prefix constructs	2019-03-18 20:43:20 -04:00
Eddie Hung	ed32119d13	Fix shregmap to correctly recognise non chain users; cleanup	2019-03-18 16:12:19 -07:00
Eddie Hung	b94db54664	shiftx NULL pointer check	2019-03-18 13:35:54 -07:00
Clifford Wolf	90bce04156	Update issue template ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-17 12:53:47 +01:00
Clifford Wolf	6aae502a36	Update issue template ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-17 12:44:23 +01:00
Eddie Hung	d6d9ef0fee	Cleanup	2019-03-16 12:49:46 -07:00
Eddie Hung	fadeadb8c8	Only accept <128 for variable length, only if $shiftx exclusive	2019-03-16 08:51:13 -07:00
Clifford Wolf	5481205094	Merge pull request #877 from FelixVi/master ... Add note about test requirements in README	2019-03-16 14:19:02 +01:00
Felix Vietmeyer	a71c38f163	Add note about test requirements in README	2019-03-16 06:20:59 -06:00
Eddie Hung	29a8d4745e	Cleanup synth_xilinx	2019-03-15 23:01:40 -07:00
Eddie Hung	06f8f2654a	Working	2019-03-15 19:13:40 -07:00
Clifford Wolf	aa65d3fe65	Improve mix of src/wire/wirebit coverage in "mutate -list" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-16 00:55:46 +01:00
Clifford Wolf	3fb363ec8c	Merge pull request #876 from YosysHQ/clifford/fmcombine ... Add fmcombine pass	2019-03-16 00:17:15 +01:00
Clifford Wolf	dacaebae35	Add "fmcombine -fwd -bwd -nop" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-15 21:45:37 +01:00
Clifford Wolf	370db33a4c	Add fmcombine pass ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-15 20:46:17 +01:00
Clifford Wolf	b5cf8c9442	Merge pull request #875 from YosysHQ/clifford/mutate ... Add "mutate" pass	2019-03-15 00:51:40 +01:00
Clifford Wolf	9820ed6531	Disable realmath tests ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-15 00:48:23 +01:00
Clifford Wolf	d1985f6a22	Improvements in "mutate" list-reduce algorithm ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-15 00:18:31 +01:00
Clifford Wolf	27a5d9c91e	Add "mutate -cfg", improve pick_cover behavior ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 23:20:41 +01:00
Clifford Wolf	4d304e3da7	Add a strictly coverage-driven mutation selection strategy ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 23:01:55 +01:00
Clifford Wolf	2a4263a75d	Improve "mutate" wire coverage metric ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 23:01:01 +01:00
Clifford Wolf	1b4fdbb0d8	Add more mutation types, improve mutation src cover ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 22:04:42 +01:00
Clifford Wolf	bacca57537	Fix smtbmc.py handling of zero appended steps ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 22:04:42 +01:00
Clifford Wolf	6ad5d036c5	Add "mutate" command DB reduce functionality ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 22:04:42 +01:00
Clifford Wolf	76c9c350e7	Add hashlib "<container>::element(int n)" methods ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 22:04:42 +01:00
Clifford Wolf	8e6b69d7bb	Add "mutate -mode inv", various other mutate improvements ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-14 22:04:42 +01:00