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Author	SHA1	Message	Date
Clifford Wolf	0f9ca49dc6	Added passing of various options to vhdl2verilog	2014-07-12 10:02:39 +02:00
Clifford Wolf	847e2ee4a1	Use "verilog -sv" to parse .sv files	2014-07-11 13:10:51 +02:00
Clifford Wolf	55a1b8dbac	Fixed processing of initial values for block-local variables	2014-07-11 13:05:53 +02:00
Clifford Wolf	3b52121d32	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	1c81ab49e7	small changes in presentation	2014-07-02 06:16:31 +02:00
Clifford Wolf	d26561cc44	Tiny fix in presentation	2014-06-29 09:27:03 +02:00
Clifford Wolf	3a3f5d5923	Progress in presentation	2014-06-29 09:14:49 +02:00
Clifford Wolf	89c85cac41	Added links to some liberty files to README	2014-06-28 12:11:42 +02:00
Clifford Wolf	3e96ce8680	Progress in presentation	2014-06-26 22:05:39 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	4fc43d1932	More found_real-related fixes to AstNode::detectSignWidthWorker	2014-06-24 15:08:48 +02:00
Clifford Wolf	a7aea17959	Progress in presentation	2014-06-22 12:50:29 +02:00
Clifford Wolf	3345fa0bab	Little steps in realmath test bench	2014-06-21 21:43:04 +02:00
Clifford Wolf	65b2e9c064	fixed signdness detection for expressions with reals	2014-06-21 21:41:13 +02:00
Clifford Wolf	072604f30f	fixed typo	2014-06-21 21:13:18 +02:00
Clifford Wolf	b18fa95d2f	Progress in presentation	2014-06-21 16:33:33 +02:00
Clifford Wolf	1c85584fe5	Do not create $dffsr cells with no-op resets in proc_dff	2014-06-19 12:29:29 +02:00
Clifford Wolf	df76da8fd7	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:49:59 +02:00
Clifford Wolf	80e4594695	Added AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:39:25 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	88470283c9	Little steps in realmath test bench	2014-06-16 15:21:08 +02:00
Clifford Wolf	6c17d4f242	Improved ternary support for real values	2014-06-16 15:12:24 +02:00
Clifford Wolf	82bbd2f077	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	2014-06-16 15:05:37 +02:00
Clifford Wolf	0c4c79c4c6	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	2014-06-16 15:02:40 +02:00
Clifford Wolf	5bfe865cec	Added found_real feature to AstNode::detectSignWidth	2014-06-16 15:00:57 +02:00
Clifford Wolf	b1b96d199f	Added more calls to "hierarchy" to README file	2014-06-15 11:51:51 +02:00
Clifford Wolf	398482eced	Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)	2014-06-15 09:39:22 +02:00
Clifford Wolf	a4ec19c25c	Added tests/realmath to "make test"	2014-06-15 09:31:03 +02:00
Clifford Wolf	4d1df128fa	Improved AstNode::realAsConst for large numbers	2014-06-15 09:27:09 +02:00
Clifford Wolf	656685fa31	Improved realmath test bench	2014-06-15 08:48:41 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	48dc6ab98d	Improved AstNode::asReal for large integers	2014-06-15 08:38:31 +02:00
Clifford Wolf	11d2add1b9	improved realmath test bench	2014-06-14 21:00:51 +02:00
Clifford Wolf	149fe83a8d	improved (fixed) conversion of real values to bit vectors	2014-06-14 21:00:51 +02:00
Clifford Wolf	39eb347c67	progress in realmath test bench	2014-06-14 19:56:22 +02:00
Clifford Wolf	d5765b5e14	Fixed relational operators for const real expressions	2014-06-14 19:33:58 +02:00
Clifford Wolf	ebe2d73330	added first draft of real math testcase generator	2014-06-14 19:24:01 +02:00
Clifford Wolf	1a487303a0	Progress in presentation	2014-06-14 16:45:16 +02:00
Clifford Wolf	22a998903b	Added %D and %c select commands	2014-06-14 16:19:32 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	406f86a91e	Added realexpr.v test case	2014-06-14 12:01:17 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	fc7b6d172a	Implemented more real arithmetic	2014-06-14 11:27:05 +02:00
Clifford Wolf	442a8e2875	Implemented basic real arithmetic	2014-06-14 08:51:22 +02:00
Clifford Wolf	9dd16fa41c	Added real->int convertion in ast genrtlil	2014-06-14 07:44:19 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	9a6cd64fc2	Now we are in Yoys 0.3.0+ development	2014-06-08 15:31:27 +02:00
Clifford Wolf	ca125bf41b	Tagging Yosys 0.3.0	2014-06-08 15:28:36 +02:00