7 commits

Author	SHA1	Message	Date
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	91704a7853	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)	2014-03-11 14:24:24 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	66bc46b30b	Improved FSM one-hot encoding, added binary encoding	2013-05-24 14:39:19 +02:00
Clifford Wolf	a338d1a082	Added help messages for fsm_* passes	2013-03-01 12:35:12 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00