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Code Activity
1347 commits 91 branches 52 tags 61 MiB
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8 commits

Author SHA1 Message Date
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 456ae31a8a Added "rename -hide" command 2014-01-02 20:23:34 +01:00
Clifford Wolf e729857647 Improved handling of private names in opt_clean and rename commands 2013-08-07 18:39:49 +02:00
Clifford Wolf a6aeb3dbf0 Added renaming of wires and cells to "rename" command 2013-06-19 16:55:43 +02:00
Clifford Wolf 95e937438f Added "rename" command 2013-06-10 12:37:22 +02:00