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10815 commits 121 branches 59 tags 69 MiB
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Author SHA1 Message Date
Eddie Hung
48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
1138-4EB
36c80cf456 dockerfile: use 'python:3-slim-buster' base image 2019-08-07 20:07:45 +02:00
1138-4EB
99de39fc79 dockerfile: use PREFIX instead of cp 2019-08-07 20:07:45 +02:00
Jim Lawson
5e8a98c8fd Merge branch 'master' into firrtl_err_on_unsupported_cell 
# Conflicts:
#	backends/firrtl/firrtl.cc
 2019-08-07 10:14:45 -07:00
Eddie Hung
58e512ab70 Add comment 2019-08-07 09:54:27 -07:00
Eddie Hung
f20acbc813 Revert "Add TODO" 
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
 2019-08-07 09:54:27 -07:00
Eddie Hung
789585a744 Add TODO 2019-08-07 09:54:27 -07:00
Eddie Hung
8a8c1d7857 Compute box_lookup just once 2019-08-07 09:54:27 -07:00
Eddie Hung
03ec8d6551 Run "clean" on mapped_mod in its own design 2019-08-07 09:54:27 -07:00
Eddie Hung
3090da2d98 Run "clean -purge" on holes_module in its own design 2019-08-07 09:54:27 -07:00
David Shah
5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
Clifford Wolf
9260e97aa2 Automatically prune init attributes in verific front-end, fixes #1237 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 15:31:49 +02:00
David Shah
a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
David Shah
fe95807f16 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 13:09:12 +01:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
Clifford Wolf
4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Clifford Wolf
679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231 
Fix handling of functions/tasks without top-level begin-end block
 2019-08-07 12:14:54 +02:00
Clifford Wolf
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check 
Be less aggressive with running design->check()
 2019-08-07 12:14:41 +02:00
Clifford Wolf
f1ac998bb4
Merge pull request #1257 from YosysHQ/clifford/cellcosts 
Redesign of cell cost API
 2019-08-07 12:13:50 +02:00
David Shah
607c7fa7e1 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 10:56:32 +01:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix 
Improved JSON attr/param encoding
 2019-08-07 10:40:38 +01:00
Clifford Wolf
338f6765eb Tweak default gate costs, cleanup "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 10:25:51 +02:00
Bogdan Vukobratovic
067b44938c Fix wrong results when opt_share called before opt_clean 2019-08-07 09:30:58 +02:00
1138-4EB
5e2919de02 dockerfile: add ARG IMAGE, use three stages 2019-08-07 05:38:09 +02:00
1138-4EB
3463511601 dockerfile: reduce number of COPY layers 2019-08-07 05:38:01 +02:00
1138-4EB
1f801993e3 dockerfile: DEBIAN_FRONTEND should not be permanent 2019-08-07 05:37:52 +02:00
Eddie Hung
ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung
234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung
e5be9ff871 Fix spacing 2019-08-06 16:47:55 -07:00
Eddie Hung
c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung
e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung
a6bc9265fb RTLIL::S{0,1} -> State::S{0,1} 2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf
100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Eddie Hung
43081337fa Cleanup opt_expr.cc 2019-08-06 16:04:21 -07:00
Eddie Hung
2d1b517b01 Add signed opt_expr tests 2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22 Add signed test 2019-08-06 15:38:43 -07:00
Eddie Hung
bfc7164af7 Move LSB-trimming functionality from wreduce to opt_expr 2019-08-06 15:25:50 -07:00
Eddie Hung
84f52aee0d Add SigSpec::extract_end() convenience function 2019-08-06 15:25:11 -07:00
Eddie Hung
0b56be8c56 Restore original SigSpec::extract() 2019-08-06 15:24:55 -07:00
Eddie Hung
51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah
8110fb9266
Merge pull request #1232 from YosysHQ/dave/write_gzip 
Add support for writing gzip-compressed files
 2019-08-06 19:05:35 +01:00
David Shah
c43b0c4b49 [wip] DSP48E1 sim model improvements 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 18:47:18 +01:00
Clifford Wolf
95a6582f34 Be less aggressive with running design->check() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 19:21:37 +02:00
David Shah
3a3da678ad Add test for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
David Shah
27360ceda6 Add support for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Clifford Wolf
f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00