490 commits

Author	SHA1	Message	Date
Larry Doolittle	022f570563	Keep gcc from complaining about uninitialized variables	2015-08-14 23:26:49 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	4513ff1b85	Fixed nested mem2reg	2015-07-29 16:37:08 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	13983e8318	Fixed handling of parameters with reversed range	2015-06-08 14:03:06 +02:00
Clifford Wolf	99b8746d27	Fixed signedness of genvar expressions	2015-05-29 20:08:00 +02:00
Clifford Wolf	1f1deda888	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
Clifford Wolf	d5ce9a32ef	Added deep recursion warning to AST simplify	2015-02-20 10:33:20 +01:00
Clifford Wolf	dc1a0f06fc	Parser support for complex delay expressions	2015-02-20 10:21:36 +01:00
Clifford Wolf	e9368a1d7e	Various fixes for memories with offsets	2015-02-14 14:21:15 +01:00
Clifford Wolf	7f1a1759d7	Added "read_verilog -nomeminit" and "nomeminit" attribute	2015-02-14 11:21:12 +01:00
Clifford Wolf	a8e9d37c14	Creating $meminit cells in verilog front-end	2015-02-14 10:49:30 +01:00
Clifford Wolf	cd919abdf1	Added AstNode::simplify() recursion counter	2015-02-13 12:33:12 +01:00
Clifford Wolf	2a9ad48eb6	Added ENABLE_NDEBUG makefile options	2015-01-24 12:16:46 +01:00
Clifford Wolf	df9d096a7d	Ignoring more system task and functions	2015-01-15 13:08:19 +01:00
Clifford Wolf	a588a4a5c9	Fixed handling of "input foo; reg [0:0] foo;"	2015-01-15 12:53:12 +01:00
Clifford Wolf	8e8e791fb5	Consolidate "Blocking assignment to memory.." msgs for the same line	2015-01-15 12:41:52 +01:00
Clifford Wolf	90bc71dd90	dict/pool changes in ast	2014-12-29 03:11:50 +01:00
Clifford Wolf	12ca6538a4	Fixed mem2reg warning message	2014-12-27 03:26:30 +01:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
Clifford Wolf	37aa2e02db	AST simplifier: optimize constant AST_CASE nodes before recursively descending	2014-10-29 08:29:51 +01:00
Clifford Wolf	c4a2b3c1e9	Improvements in $readmem[bh] implementation	2014-10-26 23:29:36 +01:00
Clifford Wolf	70b2efdb05	Added support for $readmemh/$readmemb	2014-10-26 20:33:10 +01:00
Clifford Wolf	84ffe04075	Fixed various VS warnings	2014-10-18 15:20:38 +02:00
William Speirs	fda52f05f2	Wrapped math in int constructor	2014-10-17 11:28:14 +02:00
Clifford Wolf	6b05a9e807	Fixed handling of invalid array access in mem2reg code	2014-10-16 00:44:23 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	48b00dccea	Another $clog2 bugfix	2014-09-08 12:25:23 +02:00
Clifford Wolf	680eaaac41	Fixed $clog2 (off by one error)	2014-09-06 19:31:04 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	ad146c2582	Fixed small memory leak in ast simplify	2014-08-21 17:33:40 +02:00
Clifford Wolf	6c5cafcd8b	Added support for DPI function with different names in C and Verilog	2014-08-21 17:22:04 +02:00
Clifford Wolf	490d7a5bf2	Fixed memory leak in DPI function calls	2014-08-21 13:09:47 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	640d9fc551	Added "via_celltype" attribute on task/func	2014-08-18 14:29:30 +02:00
Clifford Wolf	acb435b6cf	Added const folding of AST_CASE to AST simplifier	2014-08-18 00:02:30 +02:00
Clifford Wolf	85e3cc12ac	Fixed handling of task outputs	2014-08-14 22:26:10 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	0129d41efa	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	48822e79a3	Removed left over debug code	2014-07-28 19:38:30 +02:00
Clifford Wolf	ec58965967	Fixed part selects of parameters	2014-07-28 19:24:28 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	309d64d46a	Fixed two memory leaks in ast simplify	2014-07-25 13:24:10 +02:00
Clifford Wolf	20a7965f61	Various small fixes (from gcc compiler warnings)	2014-07-23 20:45:27 +02:00