Benedikt Tutzer
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e7880bab20
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removed debug output from make
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2018-10-25 15:06:55 +02:00 |
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Benedikt Tutzer
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a13cba31c9
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removed deletes
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2018-10-25 15:06:26 +02:00 |
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Clifford Wolf
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db676957a0
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Merge pull request #678 from whentze/master
Fix unhandled std::out_of_range in run_frontend() due to integer underflow
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2018-10-25 13:23:26 +02:00 |
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Clifford Wolf
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5ab58d4930
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Fix minor typo in error message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-25 13:20:00 +02:00 |
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Clifford Wolf
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6cd5b8b76b
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Merge pull request #679 from udif/pr_syntax_error
More meaningful SystemVerilog/Verilog parser error messages
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2018-10-25 13:18:59 +02:00 |
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Benedikt Tutzer
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05a9adfdeb
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added py_wrap_generator
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2018-10-25 12:27:56 +02:00 |
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Udi Finkelstein
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536ae16c3a
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
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2018-10-25 02:37:56 +03:00 |
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Clifford Wolf
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7703be045a
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Merge pull request #677 from daveshah1/ecp5_dsp
ecp5: Add blackboxes for MULT18X18D and ALU54B
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2018-10-23 19:18:45 +02:00 |
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whentze
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9ed77f5ba8
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fix unhandled std::out_of_range when calling yosys with 3-character argument
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2018-10-22 19:40:22 +02:00 |
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David Shah
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b65932edc4
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ecp5: Remove DSP parameters that don't work
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-22 16:20:38 +01:00 |
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rafaeltp
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f8b97e21f3
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using [i] to access individual bits of SigSpec and merging bits into a tmp Sig before setting the port to new signal
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2018-10-21 11:32:44 -07:00 |
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David Shah
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101f5234ff
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ecp5: Add DSP blackboxes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-21 19:27:02 +01:00 |
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rafaeltp
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7b964bfb83
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cleaning up for PR
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2018-10-20 18:02:59 -07:00 |
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rafaeltp
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ce069830c5
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fixing code style
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2018-10-20 17:57:26 -07:00 |
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rafaeltp
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0ad4321781
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solves #675
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2018-10-20 17:50:21 -07:00 |
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rafaeltp
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f25d0de6f8
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Merge pull request #1 from YosysHQ/master
updating
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2018-10-20 17:01:09 -07:00 |
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Clifford Wolf
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23b69ca32b
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Improve read_verilog range out of bounds warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-20 23:48:53 +02:00 |
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Clifford Wolf
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f3de732fb4
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Merge pull request #674 from rubund/feature/svinterface_at_top
Support for SystemVerilog interfaces as ports in the top level module + test case
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2018-10-20 23:28:09 +02:00 |
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Ruben Undheim
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436e3c0a7c
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Refactor code to avoid code duplication + added comments
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2018-10-20 16:06:48 +02:00 |
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Ruben Undheim
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397dfccb30
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Support for SystemVerilog interfaces as a port in the top level module + test case
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2018-10-20 11:58:25 +02:00 |
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Ruben Undheim
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d9a4381012
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Fixed memory leak
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2018-10-20 11:57:39 +02:00 |
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Clifford Wolf
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11c8a9eb96
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Merge pull request #673 from daveshah1/ecp5_improve
Small ECP5 improvements
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2018-10-19 17:32:42 +02:00 |
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David Shah
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d29b517fef
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ecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 15:16:40 +01:00 |
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David Shah
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677b8ed3ca
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ecp5: Add latch inference
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 15:16:40 +01:00 |
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Clifford Wolf
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6514443a5c
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Merge pull request #672 from daveshah1/fix_bram
memory_bram: Reset make_outreg when growing read ports
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2018-10-19 16:09:11 +02:00 |
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David Shah
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3420ae5ca5
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memory_bram: Reset make_outreg when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 14:46:31 +01:00 |
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Clifford Wolf
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2e32d05eab
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Merge pull request #671 from rafaeltp/master
adding offset info to memories on verilog output
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2018-10-19 13:05:51 +02:00 |
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Clifford Wolf
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2a104b29fd
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Merge pull request #670 from rubund/feature/basic_svinterface_test
Basic test for checking correct synthesis of SystemVerilog interfaces
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2018-10-19 13:03:38 +02:00 |
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rafaeltp
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c7770d9eea
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adding offset info to memories
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2018-10-18 16:22:33 -07:00 |
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rafaeltp
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609f46eeb7
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adding offset info to memories
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2018-10-18 16:20:21 -07:00 |
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Ruben Undheim
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d5aac2650f
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Basic test for checking correct synthesis of SystemVerilog interfaces
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2018-10-18 22:40:53 +02:00 |
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Clifford Wolf
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a25f370191
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Update ABC to git rev 14d985a
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-18 12:26:53 +02:00 |
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Clifford Wolf
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f24bc1ed0a
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Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
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2018-10-18 10:58:47 +02:00 |
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Clifford Wolf
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24a5c65856
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Merge pull request #657 from mithro/xilinx-vpr
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
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2018-10-18 10:54:03 +02:00 |
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Clifford Wolf
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93d99559ef
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Merge pull request #664 from tklam/ignore-verilog-protect
Ignore protect endprotect
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2018-10-18 10:52:07 +02:00 |
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Clifford Wolf
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22d9535a24
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Update ABC to git rev c5b48bb
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-17 12:23:50 +02:00 |
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Clifford Wolf
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6ca493b88c
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Minor code cleanups in liberty front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-17 12:23:36 +02:00 |
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Clifford Wolf
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8395c18cb5
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Merge pull request #660 from tklam/parse-liberty-detect-ff-latch
Handling ff/latch in liberty files
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2018-10-17 12:21:17 +02:00 |
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Clifford Wolf
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f4ad05e133
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Merge pull request #663 from aman-goel/master
Update to .smv backend
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2018-10-17 12:18:57 +02:00 |
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Clifford Wolf
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6b06876cf1
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Merge pull request #658 from daveshah1/ecp5_bram
ECP5 BRAM inference
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2018-10-17 12:16:23 +02:00 |
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Clifford Wolf
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08be796cb8
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Merge pull request #641 from tklam/master
Fix issue #639
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2018-10-17 12:15:14 +02:00 |
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Clifford Wolf
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38dbb44fa0
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Merge pull request #638 from udif/pr_reg_wire_error
Fix issue #630
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2018-10-17 12:13:18 +02:00 |
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Clifford Wolf
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debc0d3515
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We have 2018 now
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-16 16:51:58 +02:00 |
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Clifford Wolf
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6e00c217ae
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After release is before release
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-16 16:44:58 +02:00 |
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Clifford Wolf
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4d4665b23a
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Merge branch 'yosys-0.8-rc'
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2018-10-16 16:40:10 +02:00 |
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Clifford Wolf
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5706e90802
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Yosys 0.8
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-16 16:22:16 +02:00 |
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argama
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097da32e1a
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ignore protect endprotect
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2018-10-16 21:33:37 +08:00 |
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Clifford Wolf
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500726781b
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Update command reference manual
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-10-16 15:28:37 +02:00 |
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David Shah
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df4bfa0ad6
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ecp5: Disable LSR inversion
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-16 12:48:39 +01:00 |
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Aman Goel
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749b3ed62a
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Minor update
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2018-10-15 13:54:12 -04:00 |
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