Marcelina Kościelnicka
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0aad88a2fb
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Add clean_zerowidth pass, use it for Verilog output.
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.
See #3103.
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2021-12-12 19:56:50 +01:00 |
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