mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 17:45:33 +00:00
Code Activity
7555 commits 96 branches 53 tags 45 MiB
Commit graph

7555 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eddie Hung
082a01954b Revert "Output "h" extension only if boxes" 
This reverts commit 399ac760ff.
 2019-08-28 17:30:54 -07:00
Eddie Hung
070f3ac561 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:29:25 -07:00
Eddie Hung
d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung
2421cb3fed Add arrival times for HX devices 2019-08-28 17:21:37 -07:00
Eddie Hung
e4f89e01b5 Specify ice40 family to cells_sim.v using define 2019-08-28 17:21:12 -07:00
Eddie Hung
345a572449 Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival 2019-08-28 17:19:02 -07:00
Eddie Hung
2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung
0af64df10c Account for D port being a constant 2019-08-28 15:32:38 -07:00
Eddie Hung
a45c09c8d1 Account for D port being a constant 2019-08-28 15:31:55 -07:00
Eddie Hung
1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung
b8a9f73089 Comment out *.sh used for testbenches as we have no more 2019-08-28 12:36:20 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch 
Add $dlatch support to async2sync
 2019-08-28 12:36:06 -07:00
Eddie Hung
87d5d9b8c8 Use equiv for memory and dpram 2019-08-28 12:30:35 -07:00
Eddie Hung
ebd0a1875b Use equiv_opt for latches 2019-08-28 12:21:15 -07:00
Eddie Hung
32eef26ee2 Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40 2019-08-28 12:18:32 -07:00
Eddie Hung
52c4655de3 No need to replace Q of slice since $shiftx is autoremove-d 2019-08-28 11:06:11 -07:00
Eddie Hung
9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Eddie Hung
11e3eb1009 More cleanup 2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02 More cleanup 2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b Do not use default_params dict, hardcode default values, cleanup 2019-08-28 10:06:40 -07:00
Eddie Hung
64ea147236 Add .gitignore 2019-08-28 09:55:34 -07:00
Eddie Hung
2f493fb465 Use test_pmgen for xilinx_srl 2019-08-28 09:55:09 -07:00
Eddie Hung
c3e9627afe Always generate if no match 2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831 Rename test_pmgen arg xilinx_srl.{fixed,variable} 2019-08-28 09:27:03 -07:00
Eddie Hung
2e9e745efa Do not simplemap for variable test 2019-08-28 09:26:08 -07:00
Eddie Hung
975aaf190f Add xilinx_srl test 2019-08-28 09:24:19 -07:00
Eddie Hung
ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Clifford Wolf
c84fef92df
Merge pull request #1335 from YosysHQ/clifford/paramap 
Add "paramap" pass
 2019-08-28 10:35:47 +02:00
Clifford Wolf
47ffbf554e Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c Add "paramap" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73 Add $dlatch support to async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 09:45:22 +02:00
SergeyDegtyar
fe58790f37 Revert "Add tests for ecp5" 
This reverts commit 2270ead09f.
 2019-08-28 09:49:58 +03:00
SergeyDegtyar
2270ead09f Add tests for ecp5 2019-08-28 09:47:03 +03:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Marcin Kościelnicki
d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung
eab3c1432b
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap 
Add clock buffer insertion pass, improve iopadmap.
 2019-08-27 10:19:27 -07:00
Eddie Hung
28133432be Ignore all 1'bx in (* init *) 2019-08-27 09:24:59 -07:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
SergeyDegtyar
980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
SergeyDegtyar
134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
David Shah
fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
SergeyDegtyar
aad9bad326 Add tests for macc and rom; 
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
 2019-08-27 13:56:26 +03:00
Clifford Wolf
fdbcf78909 Add "make bumpversion" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-27 10:15:25 +02:00