Jim Lawson
34153adef4
Append (instead of over-writing) EXTRA_FLAGS
2019-02-15 11:56:51 -08:00
Jim Lawson
fc1c9aa11f
Update cells supported for verilog to FIRRTL conversion.
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Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
2019-02-15 11:14:17 -08:00
Clifford Wolf
9666cca9dd
Remove asicworld tests for (unsupported) switch-level modelling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-27 09:17:02 +01:00
Eric Smith
f4240cc8a4
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
Clifford Wolf
8e9e793126
Some fixes in tests/asicworld/*_tb.v
2016-05-20 17:13:11 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
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Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
ad8efeb13f
Fixed CRLF line endings
2015-08-13 09:35:00 +02:00
Clifford Wolf
08ad5409a2
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
2015-08-13 09:30:20 +02:00
Clifford Wolf
d58c3eca3a
Some test related fixes
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(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
88db09255b
Added autotest -e (do not use -noexpr on write_verilog)
2014-08-30 18:34:07 +02:00
Clifford Wolf
7d98645fe8
Added "make -j{N}" support to "make test"
2014-07-30 19:23:26 +02:00
Clifford Wolf
964a67ac41
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
Clifford Wolf
a4ec19c25c
Added tests/realmath to "make test"
2014-06-15 09:31:03 +02:00
Clifford Wolf
cc05404128
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
2013-05-24 15:15:59 +02:00
Clifford Wolf
2d9cbd3b02
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00
