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Code Activity
9006 commits 121 branches 59 tags 72 MiB
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4 commits

Author SHA1 Message Date
Claire Wolf
a7cc4673c3 Fix partsel expr bit width handling and add test case 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-08 16:12:12 +01:00
Clifford Wolf
27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf
50f22ff30c Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
Clifford Wolf
92035fb38e Implemented indexed part selects 2013-11-20 13:05:27 +01:00