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7059 commits 119 branches 55 tags 52 MiB
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3 commits

Author SHA1 Message Date
Adam Izraelevitz
794cec0016 More progress on Firrtl backend. 
Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
 2017-02-13 11:17:53 -08:00
Clifford Wolf
e01382739d More progress in FIRRTL back-end 2016-11-18 02:41:29 +01:00
Clifford Wolf
c051115e03 Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00