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16 commits

Author SHA1 Message Date
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere. 
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
 2020-08-26 17:29:32 +00:00
whitequark fbb346ea91 flatten: preserve original object names via hdlname attribute. 2020-06-08 20:19:41 +00:00
whitequark efa7424fb9 Restrict RTLIL::IdString to not contain whitespace or control chars. 
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
 2020-05-29 06:43:18 +00:00
whitequark 161eba253f manual: explain RTLIL::Wire::{upto,offset}. 2020-02-09 14:54:07 +00:00
whitequark 9251c000e8 manual: explain the purpose of sync always. 2019-07-02 17:10:13 +00:00
whitequark addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
whitequark a9ff81dd82 manual: document $meminit cell and memory_* passes. 2018-12-20 04:54:31 +00:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Anthony J. Bentley 154c9f8b51 Typos and grammar fixes through chapter 4. 2014-05-02 03:08:40 -06:00
Clifford Wolf 6c3d767976 presentation progress 2014-02-03 16:26:27 +01:00
Clifford Wolf 647c23b7b7 Updated manual 2013-09-15 11:41:05 +02:00
Clifford Wolf 36c39cbd04 Added RTLIL and Liberty syntax highlighting to manual 2013-07-25 14:00:16 +02:00
Clifford Wolf 61ed6b32d1 Added Yosys Manual 2013-07-20 15:19:12 +02:00