Emil J
61a6567b9f
Merge pull request #4789 from YosysHQ/emil/sklansky-adder
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Add a Sklansky option for `$lcu` mapping
2024-12-03 11:33:13 +01:00
Emil J. Tywoniak
fe64a714a9
techmap: add a Sklansky option for $lcu mapping
2024-12-02 11:34:58 +01:00
Emil J. Tywoniak
ebd7f2b366
techlibs: add _TECHMAP_DO_ to Han-Carlson adder
2024-12-02 09:54:24 +01:00
Emil J. Tywoniak
4bf3677640
techmap: set Han-Carlson adder priority consistent with Kogge-Stone
2024-11-28 23:54:00 +01:00
Emil J. Tywoniak
6c78bd3637
techmap: add a Han-Carlson option for $lcu mapping
2024-11-28 15:33:21 +01:00
Krystine Sherwin
27b8b4e81e
Docs: Fix missing groups
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$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
2024-10-15 11:08:30 +13:00
Krystine Sherwin
1513366f21
Docs: Adding mux cell descriptions
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Also making ver2 cell descriptions consistently spaced.
2024-10-15 07:37:34 +13:00
Krystine Sherwin
dfe803b5c6
Docs: Comments from @jix
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- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor
2024-10-15 07:37:20 +13:00
Krystine Sherwin
4d84d7e69f
simlib.v: Add x-output tag
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Also a few extra cell help texts.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
ed92374263
simlib.v: Update case equality operators to v2
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Also tag as x-aware cells and add titles.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
b1025dbaa6
cellhelp.py: Cells can have tags
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Tags are added to the list of properties when exporting to `cells.json`.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
f70a66f5b3
Docs: Assert cell has group
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Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.
2024-10-15 07:35:40 +13:00
Krystine Sherwin
5c4f7b4deb
Docs: $eqx aka case equality
2024-10-15 07:35:40 +13:00
Krystine Sherwin
596d914ead
simcells: Apply group tags
2024-10-15 07:35:40 +13:00
Krystine Sherwin
78b9dbd4ea
Docs: Assign remaining word cells to groups
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Move todos to correct place.
Add todo for x-prop cells.
2024-10-15 07:35:40 +13:00
Krystine Sherwin
1374fc2e2b
cellref: Deprecate cell_library.rst
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Most of the word/coarse level cells have an assigned group and individual page.
The gate/fine level cells are all on one page.
Fix links to `cell_library.rst`.
2024-10-15 07:34:52 +13:00
Krystine Sherwin
04b0ae540d
cellref: Move default help message to register.cc
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Drop the default help message from rst while still displaying it on the command line.
Fix command line formatting for older style help messages.
2024-10-15 07:31:47 +13:00
Krystine Sherwin
c662529316
Docs: Move binary operators to cell appendix
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Add binary group tag to relevant cells.
Remove content from `cell_library.rst` that is already moved.
2024-10-15 07:31:47 +13:00
Krystine Sherwin
7c5b10fe50
cellref: Add json dump
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New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
2024-10-15 07:25:27 +13:00
Krystine Sherwin
06e5e18371
simlib.v: Autolink referenced cells in alu
2024-10-15 07:23:45 +13:00
Krystine Sherwin
21747c468c
Docs: Improve cell_help usage
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- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
reporting errors for any cells defined in `cell_types` but not
`cell_help_messages`.
2024-10-15 07:23:45 +13:00
Krystine Sherwin
57cd8d29db
cellhelp: Add default format parse for simcells
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Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
a2b2904ed8
cellhelp: Add source line to help
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Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
784292626e
cellhelp: Rename short_desc to title
2024-10-15 07:16:39 +13:00
Krystine Sherwin
4662476ec8
Docs: Test $alu with v2 help format
2024-10-15 07:16:39 +13:00
Krystine Sherwin
600149a824
Docs: Add back message for empty help
2024-10-15 07:16:39 +13:00
Krystine Sherwin
6bbe763845
Docs: Put cell library help strings into a struct
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Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
2024-10-15 07:16:39 +13:00
Martin Povišer
9018d06a33
quicklogic: Avoid carry chains in division mapping
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The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.
For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
2024-09-19 12:18:47 +02:00
Martin Povišer
eeffca9470
simlib: Add $buf disclaimer
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
4d469f461b
Add coarse-grain $buf buffer cell type
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
NachtSpyder04
aa60255e0e
update help messages that went beyond line length limit
2024-08-18 20:27:35 +05:30
Saish Karole
34aabd56cc
Apply suggestions from code review
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Co-authored-by: Martin Povišer <povik@cutebit.org>
2024-08-18 20:12:53 +05:30
Saish Karole
d80d4dc51c
[Docs]:Add new cell type help messages ( #1 )
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* add shift operators description
* update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators
2024-08-17 15:47:00 +05:30
Martin Povišer
dc746080f5
Merge pull request #4298 from povik/kogge-stone
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techmap: Add a Kogge-Stone option for `$lcu` mapping
2024-04-08 16:46:06 +02:00
Martin Povišer
5f4d13ee3f
techmap: Note down iteration in Kogge-Stone
2024-04-08 16:45:40 +02:00
Emil J. Tywoniak
9510293a94
fixup
2024-04-04 18:16:58 +02:00
Emil J. Tywoniak
a580a7c82c
docs: Document $macc
2024-04-03 20:37:54 +02:00
Martin Povišer
bc087f91ed
techmap: Fix using overwritten results in Kogge-Stone
2024-03-27 18:32:25 +01:00
Martin Povišer
4570d064e5
techmap: Split out Kogge-Stone into a separate file
2024-03-27 11:07:24 +01:00
Martin Povišer
c38201e15d
techmap: Add a Kogge-Stone option for $lcu mapping
2024-03-25 14:56:17 +01:00
Martin Povišer
570a8f12b5
synth: Fix out-of-sync help message
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Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
2024-03-06 14:55:43 +01:00
Martin Povišer
d2a7ce04ea
synth: Rename -inject to -extra-map
2024-03-01 10:54:51 +01:00
Martin Povišer
ba07cba6ce
synth: Introduce -inject for amending techmap
2024-02-22 17:38:48 +01:00
Martin Povišer
d77b792156
synth: Put in missing bounds check for -lut
2024-02-22 17:24:26 +01:00
Miodrag Milanović
edb95c69a9
Merge pull request #4084 from jix/scopeinfo
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$scopeinfo support
2024-02-12 09:51:22 +01:00
Martin Povišer
7a3316dd78
synth: Tweak phrasing of -booth help
2024-02-08 00:05:15 +01:00
Martin Povišer
a98d363d9d
synth: Run script in full in help mode
2024-02-08 00:05:15 +01:00
Jannis Harder
f728927307
Add builtin celltype $scopeinfo
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Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
Catherine
c7bf0e3b8f
Add new $check cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
Martin Povišer
f7d4a855c6
techlibs: Add cmp2softlogic.v to common
2023-11-13 10:42:12 +01:00
