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26 commits

Author SHA1 Message Date
Miodrag Milanovic
f35bdaa527 Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
Marcelina Kościelnicka
be9595e18f xilinx: Add RAMB4* blackboxes 2022-03-21 13:11:52 +01:00
Marcelina Kościelnicka
f2932628fc xilinx: Add some missing blackbox cells. 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
5ffb676fa9 xilinx: Regenerate cells_xtra.v using Vivado 2020.2 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka
871fc34ad4 xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
2020-12-17 03:25:07 +01:00
Marcin Kościelnicki
9b982e929c xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
Eddie Hung
090e54569a Remove RAMB{18,36}E1 from cells_xtra.py 2020-02-27 10:33:04 -08:00
Eddie Hung
1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Piotr Binkowski
62ab100c61 xilinx: mark IOBUFDSE3 IOB pin as external 2020-02-27 13:15:57 +01:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcin Kościelnicki
7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung
4eaa45091c Update some abc9_arrival times, add abc9_required times 2019-12-27 14:47:50 -08:00
Marcin Kościelnicki
8b2c9f4518 xilinx: Add simulation models for remaining CLB primitives. 2019-12-19 18:04:04 +01:00
Marcin Kościelnicki
a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Marcin Kościelnicki
2badaa9adb xilinx: Add missing blackbox cell for BUFPLL. 2019-11-29 16:56:27 +01:00
Marcin Kościelnicki
0466c48533 xilinx: Add simulation models for IOBUF and OBUFT. 2019-11-26 08:15:20 +01:00
Marcin Kościelnicki
7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*.
This adds simulation models for the following primitives:

- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
2019-11-19 01:00:58 +01:00
Marcin Kościelnicki
c4bd318e76 synth_xilinx: Merge blackbox primitive libraries.
First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.

Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included.  Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.

Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).

Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
David Shah
6769d31ddb xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
526fe4cb89 xilinx: Add simulation model for IBUFG. 2019-10-10 13:16:03 +02:00
Eddie Hung
9c23811839 Remove DSP48E1 from *_cells_xtra.v 2019-10-04 17:26:42 -07:00
Eddie Hung
5b5756b91e Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} 2019-09-30 12:52:43 +02:00
Marcin Kościelnicki
13fa873f11 Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
Marcin Kościelnicki
09ac36da60 xilinx: Make blackbox library family-dependent.
Fixes #1246.
2019-09-15 13:37:24 +02:00
Marcin Kościelnicki
3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00