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mirror of https://github.com/YosysHQ/yosys synced 2025-06-11 00:23:26 +00:00
Code Activity
15147 commits 109 branches 55 tags 46 MiB
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3 commits

Author SHA1 Message Date
Adrien Prost-Boucle
c7de531231 URAM mapping : Fix port indexes according to Yosys warnings 2025-05-09 15:09:11 +02:00
Adrien Prost-Boucle
c4a49f0c55 Create a single-port URAM mapping to support memories 2048 x 144b 2025-05-09 14:16:03 +02:00
Marcelina Kościelnicka
3b2f95953c xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00