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12 commits

Author SHA1 Message Date
Krystine Sherwin
d0b9a0cb98
sim.cc: Move cycle check
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
2025-05-12 12:48:01 +12:00
Miodrag Milanovic
ad48639cdd Start restoring memory state from VCD/FST 2022-05-04 10:41:04 +02:00
Miodrag Milanovic
2e47b61cc6 Proper scope naming from FST 2022-03-30 15:55:15 +02:00
Miodrag Milanovic
1f3423cd7d Recognize registers and set initial state for them in tb 2022-03-16 14:35:39 +01:00
Miodrag Milanovic
8be09b5b24 VCD reader support by using external tool 2022-02-28 09:09:07 +01:00
Miodrag Milanovic
fb22d7cdc4 Add support for various ff/latch cells simulation 2022-02-16 13:27:59 +01:00
Miodrag Milanovic
543feb75cb Display simulation time data 2022-01-31 10:52:47 +01:00
Miodrag Milanovic
a8d03df173 cleanup 2022-01-28 12:54:16 +01:00
Miodrag Milanovic
4f75a2ca1b Do actual compare 2022-01-28 12:50:41 +01:00
Miodrag Milanovic
3e35de2be1 Add more options and time handling 2022-01-28 10:18:02 +01:00
Miodrag Milanovic
226dc659f0 Fix tabs/spaces 2022-01-26 16:39:51 +01:00
Miodrag Milanovic
8a02616465 Add fstdata helper class 2022-01-26 10:23:38 +01:00